Chisel: fail to generate verilog while writing a simple combinational logic

Question

I want to implement operation of rotate left shift.

My chisel code :

// src/main/scala/ALU.scala

package cpu

import chisel3._

class ALU extends RawModule {
  val io = IO(new Bundle {
    val a = Input(UInt(32.W))
    val b = Input(UInt(32.W))
    val out = Output(UInt(32.W))
  })
  io.out := (io.a << io.b) | (io.a >> (32.U(32.W) - io.b))
}

// src/test/scala/test.scala

package test
import cpu._

object testCPU extends App {
  chisel3.Driver.execute(args, () => new ALU)
}

I built my project with sbt, typing test:runMain test.testCPU -td generated in sbt shell, and the output is as follows:

[info] running test.testCPU -td generated
Elaborating design...
Done elaborating.
[error]         at 
[success] Total time: 3 s, completed Nov 19, 2021, 2:55:15 AM

It generated firrtl successfully, but failed to generate verilog.

The firrtl code is as follows:

;buildInfoPackage: chisel3, version: 3.4.3, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit ALU : 
  module ALU : 
    output io : {flip a : UInt<32>, flip b : UInt<32>, out : UInt<32>}
    
    node _io_out_T = dshl(io.a, io.b) @[ALU.scala 15:19]
    node _io_out_T_1 = sub(UInt<32>("h020"), io.b) @[ALU.scala 15:51]
    node _io_out_T_2 = tail(_io_out_T_1, 1) @[ALU.scala 15:51]
    node _io_out_T_3 = dshr(io.a, _io_out_T_2) @[ALU.scala 15:36]
    node _io_out_T_4 = or(_io_out_T, _io_out_T_3) @[ALU.scala 15:28]
    io.out <= _io_out_T_4 @[ALU.scala 15:10]

escou64 · Accepted Answer · 2021-11-23 20:54:11Z

2

You are currently using the old way to generate Verilog with the execute function. Replace your object in the test.scala by:

import chisel3._

object testCPU extends App {
  (new chisel3.stage.ChiselStage).emitVerilog(new ALU, args)
}

It will not resolve your error, but the printed message will be more informative. Then we will be able to help you.

answered Nov 23, 2021 at 20:54

escou64

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