How to fix chisel test errors whit Verilator (should work with verilator * FAILED *)?

Question

I run chisel test and want to generate outputs with verilator. I couldn't find the cause of the error exactly but i think that is related to verilator. This is the part of code that execute the test. It must print some outputs and generate simulation files.

class ComplexMemoryLoadingSpec extends  FreeSpec with Matchers {
  "memory loading should be possible with complex memories" - {

    val targetDirName = "test_run_dir/complex_mem_test"
    FileUtils.makeDirectory(targetDirName)

    val path1 = Paths.get(targetDirName + "/mem_cameraman.bin")


    Files.copy(getClass.getResourceAsStream("/cameraman.bin"), path1, REPLACE_EXISTING)



    "should work with verilator" in {
      iotesters.Driver.execute(
        args = Array("--backend-name", "verilator", "--target-dir", targetDirName, "--top-name", "complex_mem_test"),
        dut = () => new HasComplexMemory(memoryDepth = 65536)
      ) { c =>
        new HasComplexMemoryTester(c)
      } should be(true)
    }
  }
}

It doesn't work and I got this errors:

[info] Done compiling.
[info] [0.005] Elaborating design...
[info] [0.515] Done elaborating.
Total FIRRTL Compile Time: 1965.5 ms
cd /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test && verilator --cc HasComplexMemory.v --assert -Wno-fatal -Wno-WIDTH -Wno-STMTDLY -O1 --top-module HasComplexMemory +define+TOP_TYPE=VHasComplexMemory +define+PRINTF_COND=!HasComplexMemory.reset +define+STOP_COND=!HasComplexMemory.reset -CFLAGS "-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h" -Mdir /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test -f /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/firrtl_black_box_resource_files.f --exe /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/HasComplexMemory-harness.cpp --trace
make: Entering directory '/home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test'
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o HasComplexMemory-harness.o /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/HasComplexMemory-harness.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o verilated_vcd_c.o /usr/local/share/verilator/include/verilated_vcd_c.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VHasComplexMemory.cpp VHasComplexMemory___024unit.cpp > VHasComplexMemory__ALLcls.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VHasComplexMemory__Trace.cpp VHasComplexMemory__Syms.cpp VHasComplexMemory__Trace__Slow.cpp > VHasComplexMemory__ALLsup.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o VHasComplexMemory__ALLcls.o VHasComplexMemory__ALLcls.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o VHasComplexMemory__ALLsup.o VHasComplexMemory__ALLsup.cpp
      Archiving VHasComplexMemory__ALL.a ...
ar r VHasComplexMemory__ALL.a VHasComplexMemory__ALLcls.o VHasComplexMemory__ALLsup.o
ranlib VHasComplexMemory__ALL.a
g++    HasComplexMemory-harness.o verilated.o verilated_vcd_c.o VHasComplexMemory__ALL.a    -o VHasComplexMemory -lm -lstdc++ 
make: Leaving directory '/home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test'
sim start on Dell at Fri Sep 27 13:38:29 2019
inChannelName: 00008431.in
outChannelName: 00008431.out
cmdChannelName: 00008431.cmd
STARTING test_run_dir/complex_mem_test/VHasComplexMemory
Enabling waves..%Error: test_run_dir/complex_mem_test/mem_a:0: $readmem file not found
Aborting...
[info] ComplexMemoryLoadingSpec:
[info] memory loading should be possible with complex memories
[info] - should work with verilator *** FAILED ***
[info]   chisel3.iotesters.TestApplicationException: test application exit - exit code 134
[info]   at chisel3.iotesters.SimApiInterface.throwExceptionIfDead(SimApiInterface.scala:98)
[info]   at chisel3.iotesters.SimApiInterface.chisel3$iotesters$SimApiInterface$$mwhile(SimApiInterface.scala:107)
[info]   at chisel3.iotesters.SimApiInterface$$anonfun$start$3.apply$mcVI$sp(SimApiInterface.scala:268)
[info]   at scala.collection.immutable.Range.foreach$mVc$sp(Range.scala:160)
[info]   at chisel3.iotesters.SimApiInterface.start(SimApiInterface.scala:266)
[info]   at chisel3.iotesters.SimApiInterface.<init>(SimApiInterface.scala:325)
[info]   at chisel3.iotesters.VerilatorBackend.<init>(VerilatorBackend.scala:295)
[info]   at chisel3.iotesters.setupVerilatorBackend$.apply(VerilatorBackend.scala:284)
[info]   at chisel3.iotesters.Driver$$anonfun$execute$1$$anonfun$apply$mcZ$sp$1.apply$mcZ$sp(Driver.scala:56)
[info]   at chisel3.iotesters.Driver$$anonfun$execute$1$$anonfun$apply$mcZ$sp$1.apply(Driver.scala:39)
[info]   ...
[info] ScalaTest
[info] Run completed in 1 minute, 41 seconds.
[info] Total number of tests run: 1
[info] Suites: completed 1, aborted 0
[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0
[info] *** 1 TEST FAILED ***
[error] Failed: Total 1, Failed 1, Errors 0, Passed 0
[error] Failed tests:
[error]     util.ComplexMemoryLoadingSpec
[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful

Can someone help me? or explain what is wrong there

Chick Markley · Accepted Answer · 2019-09-27 22:15:22Z

1

I think the problem is that it cannot find the file containing the data you would like to load into the memory. If it is a complex memory then you need to have a separate file for each distinct item in memory.

It is failing to find the file test_run_dir/complex_mem_test/mem_a I'm guessing these two lines

val path1 = Paths.get(targetDirName + "/mem_cameraman.bin")
Files.copy(getClass.getResourceAsStream("/cameraman.bin"), path1,REPLACE_EXISTING)

Are trying to place the data file where verilator can find it, but I don't think this is matching up with where the code says the file will be found.

Can you show the memory declaration and the place you specified the file name. This is definitely complicated. check out this doc on loading chisel memories

answered Sep 27, 2019 at 22:15

Chick Markley

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3 Comments

Mohamed Abou Messaad Over a year ago

Hi, I made some modifications and I found the file finally but a new error appears %Error: test_run_dir/complex_mem_test/cameraman_a:1: $readmem file syntax error I guess it has a problem with file format.

Mohamed Abou Messaad Over a year ago

I posted the code on github here is the link to check it Test Failed with chisel-testers

Chick Markley Over a year ago

I have answered your question in the issue you have created. It looks to me like you do have the location of the file correct but probably there is some problem with its contents

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