Im not quite sure how to make a module which allows the output(B) of one module to become the input of another module(C).
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It seems the OP already understands that modules have inputs and outputs. But not understanding how modules get instantiated and connections (the flow of assignments/drivers to sources) made is a very broad topic in SystemVerilog.dave_59– dave_592017-11-27 22:11:31 +00:00Commented Nov 27, 2017 at 22:11
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Duplicate of Output of a module used as input of another in verilog?Qiu– Qiu2017-11-28 06:59:44 +00:00Commented Nov 28, 2017 at 6:59
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1 Answer
1) you need to declare your modules with input and output ports
module A(input clk, input sig, output out);
.. do somethign here
endmodule
module B(input clk, output val);
... do something to generate val.
endmodule
2) you would need to create a hierarchy of instances, instantiating those modules, inside a top-level one. The latter will declare wires which should be used to connect these two:
module top(output topout);
wire clk;
wire sig;
wire out;
A a(clk, sig, topout);
B b(clk, sig);
endmodule
So, in the above example output port val of instance b of module B is assigned to the wire sig of the top-level module. The same wire sig is connected to the input port sig of the instance a of the module A.
The output port out of the insance a is also connected to the output port topout port of the top-level module.
in both cases the clk wire is connected to two input ports: instance a and instance b.
This is the basic idea.
