How to have a binary number with constant lenght

Question

I'm trying to write a test_bench for a dynamic size register. I defined a parameter variable like this and instantiated a register module:

  parameter integer regSize = 8;

  register #(.size(regSize)) R1 (
   .clock(clk),
   .reset(rst),
   .enable(enb),
   .regIn(in),
   .regOut(outp)
  );

now forexample I want to define "in" variable ( the 4th input of module )

  reg [regSize - 1: 0] in = (regSize)'b0;

I expect this works as : reg [regSize - 1: 0] in = 8'b0; But it doesn't.

I get this error:

near "'b": syntax error, unexpected BASE, expecting ';' or ','

How should I write this?

Thanks for any help.

dave_59 · Accepted Answer · 2018-03-25 14:06:01Z

2

Use the concatenation repeat structure:

reg [regSize - 1: 0] in = {regSize{1'b0}};

Or in System Verilog you can do :

reg [regSize - 1: 0] in = '0;

You might also need something similar for adding e.g. 1 to a counter with variable length:

...
counter <= counter + {{(regSize-1){1'b0}},1'b1}; // regSize>1!

As that becomes difficult to read I prefer to use a localparam :

localparam [regSize-1:0] value_1 = {{(regSize-1){1'b0}},1'b1}; // regSize>1!
   ...
   counter <= counter + value_1;

Note that it can get rather messy if you also want to have a width of 1 bit as but I assume adding 1 to a 1 bit counter is likely to be a design error.

edited Mar 25, 2018 at 14:06

dave_59

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answered Mar 24, 2018 at 14:57

Oldfart

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Comments

dave_59 · Accepted Answer · 2018-03-25 14:05:34Z

0

There is no need to pad 0's to a number in Verilog, it does that automatically for you. You can just do

reg [regSize - 1: 0] in = 0;

answered Mar 25, 2018 at 14:05

dave_59

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2 Comments

Kamran Hosseini Over a year ago

I was wondering how to assign values like 8'b11010110 to register "in"

dave_59 Over a year ago

in = 8'b11010110; It gets truncated or padded with 0's to fit the size of in. If you want that pattern replicated, then do in = {$ceil(regSize/8.0){8'b11010110}};

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