Can you use/manipulate same output/reg variable in multiple always blocks?

Can I us the variable count inside multiple always block?

Not in RTL code NO.

Is this a good design practice?

"good design practice" is not a well defined term. You might use it in a test-bench but not in the format you use. In that case you must make sure that all always conditions are mutual exclusive.

Why/Where should/should not use this method?

You could use it if you have about 10 years experience in writing code. Otherwise don't. As to "should" never!

How does the simulator/synthesizer do the calculations for that variable 'count'?

The synthesizer will refuse your code. The simulator will assign a value just as you described. Which in your code means: you have no idea which assignment is executed last so the result is unpredictable.

Does the compiler throw error if I do this?

Why ask if you can try?

I'm not a hardware designer, but this is not good. Your 3 always blocks will all infer a register and they will all drive the count signals.

You can read signals in multiple blocks, but you should only write to them in a single block.

In most cases you don't want to have multi-drivers. If you have something like a bus with multiple possible masters then you will want multi-drivers, but they need to drive the bus through tri-states and you need to ensure that the master has exclusive access.

Mixing posedge and negedge is not a good idea.

With a single block you might write something like this (which appropriate macros or parameter for UP1, DOWN1 and DOWN2).

always @(posedge clk or negedge reset_n)
begin
    if (reset_n == 1'b0)
    begin
        count <= 32'b0;
    end
    else
    begin
        case (count_control)
            UP1: count <= count + 1'b1;
            DOWN2: count <= count - 2'b10;
            DOWN1: count <= count - 1'b1;
        endcase
    end
end

No. You can't have assignments to a net from multiple always block.

Here is the synthesis result of 2 implementation in Synopsys Design Compiler

ASSIGNMENTS FROM MULTIPLE ALWAYS BLOCK.

module temp(clk, rst, x, y, op);
  input logic clk, rst;
  logic [1:0] count;
  input logic x, y;
  output logic [1:0] op;

  assign op = count;

  always @ (posedge clk) begin     
    if (x) begin 
      count <= count + 2'd1;
    end    
  end

  always @ (posedge clk) begin     
    if (y) begin 
      count <= count - 2'd2;
    end    
  end

  always @ (negedge clk) begin     
    if (x) begin 
      count <= count - 2'd1;
    end    
  end
endmodule

// Synthesis Result of elaborate command - 
Error:  /afs/asu.edu/users/k/m/s/kmshah4/temp/a.sv:16: Net 'count[1]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366)
Error:  /afs/asu.edu/users/k/m/s/kmshah4/temp/a.sv:16: Net 'count[0]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366)

ASSIGNMENTS WITH SINGLE ALWAYS BLOCK.

module temp(clk, rst, x, y, op);
  input logic clk, rst;
  logic [1:0] count;
  input logic x, y;
  output logic [1:0] op;

  assign op = count;

  always @ (clk)
  begin
    if (clk)
    begin
      case ({x, y})
        2'b01 : count <= count - 2'd2;
        2'b10 : count <= count + 2'd1;
        default : count <= count;
      endcase
    end
    else
    begin
      count <= (x) ? (count - 2'd1) : count;
    end
  end
endmodule

// Synthesis Result of elaborate command - 
Elaborated 1 design.
Current design is now 'temp'.
1