Verilog combined assignemnts

Question

Hi in Verilog what is the significance of this operation:

wire signal_A = |signal_B;

Is this possible with other logic operators?

It is a reduction OR: It OR-es all bit of B together. Thus A is high if at least one bit in B is high, A is low if all bits of B are low. Yes, you can use & or ^ too. — Oldfart
– Oldfart, Commented Jul 16, 2018 at 16:55

dave_59 · Accepted Answer · 2018-07-16 15:49:03Z

2

It's just a short-cut for

wire signal_A;
assign  signal_A = |signal_B;

IMHO, Verilog is full of unnecessary shortcuts making it more difficult to read and maintain.

answered Jul 16, 2018 at 15:49

dave_59

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Comments

cc6g11 · Accepted Answer · 2018-07-17 10:58:22Z

0

I should have been more explicit in the question.

But the answer is that this is used for logic on 2 varying width signals

wire signal_A;
wire [N:0] signal_B;

assign signal_A = |signal_B;

This is equivalent to

assign signal_A = signal_B[0] | ... | signal_B[N];

So not as verbose and explicit as VHDL, but quicker.

answered Jul 17, 2018 at 10:58

cc6g11

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