Verilog continuous assignment equivalent of always block

Question

How the always block could be replaced with a continuous assignment statement using the ‘{ }’ and ‘? :’?

module mux16to8 (input [7:0] secsa, minsa, secsb, minsb,
output reg [7:0] secs, mins,
input sela, selb, hold, seldisp,
output reg leda, ledb);
always @(*)
begin
    if (hold == 1'b1)
       if (seldisp == 1'b1) begin
        secs = secsa;
        mins = minsa;
        leda = 1'b0;
        ledb = 1'b1;
       end else begin
         secs = secsb;
         mins = minsb;
         leda = 1'b1;
         ledb = 1'b0;
    end
    else
        if (sela == 1'b1) begin
         secs = secsa;
         mins = minsa;
         leda = 1'b0;
          ledb = 1'b1;
        end else if (selb == 1'b1) begin
           secs = secsb;
           mins = minsb;
           leda = 1'b1;
           ledb = 1'b0;
          end else begin
           secs = 0;
          mins = 0;
         leda = 1'b1;
         ledb = 1'b1;
            end
     end
endmodule

I thought at something like

assign secs={seldisp?{hold?1:0}:0}?secsa:secsb
assign mins={seldisp?{hold?1:0}:0}?minsa:minsb..

I know that this is not enough because the secs and mins variables are in an always loop, so for continous assignment i should get something similar as always loop and right now i don't even know if my statements are fine.

What kind of always block? Can you give a small example of the original statement? — N8TRO
– N8TRO, Commented Apr 10, 2014 at 21:04
Why? If they are equivalent then they will synthesise to the same thing. Also you can use {}'s in your always block {a,b,c} = {d,e,f} — Will
– Will, Commented Apr 11, 2014 at 8:16

CliffordVienna · Accepted Answer · 2014-04-11 03:26:42Z

4

One solution would be this:

module mux16to8 (input [7:0] secsa, minsa, secsb, minsb,
output [7:0] secs, mins,
input sela, selb, hold, seldisp,
output leda, ledb);

assign {secs, mins, leda, ledb} =
    hold ? seldisp ? {secsa, minsa, 1'b0, 1'b1} :
                     {secsb, minsb, 1'b1, 1'b0} :
              sela ? {secsa, minsa, 1'b0, 1'b1} :
              selb ? {secsb, minsb, 1'b1, 1'b0} :
                     { 8'd0,  8'd0, 1'b1, 1'b1};

endmodule

I've used the following Yosys script to prove formal equivalence:

read_verilog q22998917a.v
rename mux16to8 mux16to8_orig

read_verilog q22998917b.v

proc; opt
miter -equiv mux16to8_orig mux16to8 miter
flatten miter;;

sat -prove trigger 0 miter

edited Apr 11, 2014 at 3:26

answered Apr 11, 2014 at 0:22

CliffordVienna

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2 Comments

Russell Over a year ago

Would you ever put something like that in real code? That looks confusing and is not intuitive IMO. I would prefer to just see the combinational always block with if statements that are easier to parse mentally.

CliffordVienna Over a year ago

@Russell: No, I would not use this in production code and would instead prefer a behavioral model as well. I was merely answering the question as it was stated.

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