VHDL Two Type Declarations In A Package Create An Error

Question

I am trying to build up a self made package for a VHDL project using Vivado and am having an error when I add more than one type declaration.

package TypeDef is
type IntCommand is (meW, meA, meO, meB);

--    type TestType is array (0 to 3) of STD_LOGIC;

type Rec is record
    inst : IntCommand;
    num1 : STD_LOGIC_VECTOR(3 downto 0);
    num2 : STD_LOGIC_VECTOR(3 downto 0);
end record Rec;

end package TypeDef;

If I comment out the line that is commented out with the 'TestType' the package is able to work all the way through to simulation. However, if I uncomment that line of code or add in any other variation of type the design has an error when attempting to simulate. The error on the elaborate step.

Cheers,

Note you do not provide a context clause for this design unit. Adding that we find several semantic errors. A redeclaration of meA in type IntCommand and an attempt to use inst as both an element of a record and a type mark. There is no visible type declaration for Inst. Show your error messages and a minimal reproducible example. — user1155120
– user1155120, Commented Sep 14, 2018 at 22:40
I changed the variable names when I uploaded the question. I didn't notice the errors I made. Thanks. — phlie
– phlie, Commented Sep 14, 2018 at 22:44
EEE Std 1076-2008 14.2 Elaboration of a design hierarchy The elaboration of a design hierarchy creates a collection of processes interconnected by nets; this collection of processes and nets can then be executed to simulate the behavior of the design. A package doesn't contain any process statements or concurrent statements with equivalents, see 11. Concurrent statements and 3. Design entities and configurations. Provide a minimal reproducible example and your actual error messages. — user1155120
– user1155120, Commented Sep 14, 2018 at 23:28

phlie · Accepted Answer · 2018-09-15 02:38:40Z

2

After searching around for the error I found it to be rather simple to fix. I only needed to edit and then save the main file. The error message found in 'elaborlate.log' was 'core.vdb needs to be re-saved since xil_defaultlib.typedef changed'.

answered Sep 15, 2018 at 2:38

phlie

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