How to use a parameter to add or remove a signal from a system verilog interface and modport

Question

Here is a snippet of some interface code that has some parameterized sizes to it. The fourth parameter, HAS_BURST is something I have experimented with, but it has only resulted in compilation errors.

Effectively I am looking for a way to ADD/REMOVE a signal from a interface based on parameter. Is there a way to have a generic interface with removable signals?

interface axi_if 
    #(parameter ID_WIDTH   = 4, 
                ADDR_WIDTH = 40,
                DATA_WIDTH = 64,
                HAS_BURST  = 0) 
    ();

logic                      aw_ready;     
logic                      aw_valid;     
logic [ID_WIDTH-1:0]       aw_bits_id;   
logic [ADDR_WIDTH-1:0]     aw_bits_addr; 
logic [7:0]                aw_bits_len;  
logic [2:0]                aw_bits_size;
generate
if (HAS_BURST)
logic [1:0]                aw_bits_burst;
endgenerate
logic [2:0]                aw_bits_size;

modport slave (  
output aw_ready,
input  aw_valid,
input  aw_bits_id,
input  aw_bits_addr,
input  aw_bits_len,
generate
if (HAS_BURST)
input  aw_bits_burst,
endgenerate
input  aw_bits_size
);

modport master (  
input  aw_ready,
output aw_valid,
output aw_bits_id,
output aw_bits_addr,
output aw_bits_len,
generate
if (HAS_BURST)
output aw_bits_burst,
endgenerate
output aw_bits_size
);
endinterface
`endif

welcome to the club. the only way to do it is ` ifdef ... endif — Serge
– Serge, Commented Mar 11, 2019 at 23:12
Do you have any requirement for using parameter explicitly? This can be done by using an ifdef macro. Just declare the signal only if macro is defined and use them based on some parameter/macro. — sharvil111
– sharvil111, Commented Mar 11, 2019 at 23:18
The usage in this case is for AXI interfaces, where there are multiple instances of AXI buses in the same design, each with different bus widths and capabilities. I was looking for a way of making parameterized instances in lieu of globalized defines. — Rich Maes
– Rich Maes, Commented Mar 12, 2019 at 3:54
Well, you could use a generate statement to switch between modports, but doing so has been specifically banned in the 2017 standard. — Matthew
– Matthew, Commented Mar 12, 2019 at 8:45

Steve K · Accepted Answer · 2019-06-14 08:21:18Z

No, there isn't. Ports aren't valid in generate blocks. Parameters can be used to asjust the width of a port but not remove it entirely. You could use an `ifdef to compile it conditionally but that's an all-or-none solution. There can't be some instances with the signal and others without it.

Having the signal unconditionally present is fine in many situations and it's the easiest way to handle this problem. Tie any unused inputs to logic 0 and unused outputs can remain unconnected.

If neither of these options work there's no other way than to define two different interfaces. Doing this by hand quickly becomes unmaintainable. If there are two variations now you can be sure a third one will be needed soon, then a fourth, a fifth... Many chip design companies have SystemVerilog code generators which create customized modules for each instance.

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