Constant not recognized within systemverilog module

Question

I tried to compile the following code:

module sample (
                  input  logic       [31:0] data_i,
                  output logic [31:0] data_o
                 );

`define SUBNORMAL 31'b0

/*Intermediate storage of input data*/
logic [15:0] data_str_0;
bit sign_0;

initial begin
  data_str_0 = data_i[31:16] ;
end

/*Assigning the sign bit*/
initial begin
sign_0 = data_str_0[15];
end

/*Exponent calculation*/
logic [4:0] exp_hf_0;
logic [7:0] exp_sf_0;

initial begin
exp_hf_0 = data_str_0 [14:10];
end

/*Adjusting the bias*/
always @(*)
begin
exp_sf_0 = exp_hf_0 + 8'd112;
end

/*Mantissa calculation*/
logic [9:0] man_hf_0;
logic [22:0] man_sf_0;

initial begin
man_hf_0 = data_str_0 [9:0];
end

always @(*)
begin
man_sf_0 = {man_hf_0,13'b0};
end

/*Packing the output*/
always @(*)
begin
if (exp_sf_0 == 5'b0 && man_sf_0 != 10'b0)
data_o = '{sign_0,SUBNORMAL};
end    

endmodule

However I am getting the following error message:

**Error: sample.sv(52): (vlog-2730) Undefined variable: 'SUBNORMAL'.

My intention is to bind the SUBNORMAL constant value with the sign_0 and assign it into data_o.

Can anyone suggest me a solution?

In C you don't need a # when you use a symbol you have defined with #define; in (System)Verilog you do need to add the backtick, as toolic says. — Matthew
– Matthew, Commented Dec 16, 2019 at 15:03
After the backtick the following error is coming. (vlog-13174) Illegal assignment pattern. The number of elements (2) doesn't match with the type's width (32). — Saikat Chatterjee
– Saikat Chatterjee, Commented Dec 17, 2019 at 13:42

dave_59 · Accepted Answer · 2019-12-16 15:37:44Z

1

To use a `define macro, you need the ` symbol in front of it.

However, I suggest that you use a parameter instead

parameter SUBNORMAL = 32'b0;

This way the parameter is scoped local to the place you want to use it.

answered Dec 16, 2019 at 15:37

dave_59

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