I am starting in FPGA coding, and one of my first exercises is to code a full adder. I am using SystemVerilog to code within Vivado. My take on this is as follow:
Source:
`timescale 1ns/10ps
module challenge
(
input wire [2:0] SW,
output logic [1:0] LED
);
assign LED[0]=SW[1]^SW[0]^SW[2]; // Write the code for the Sum
assign LED[1]=(SW[1]&SW[0])|((SW[1]^SW[0])&SW[2]); // Write the code for the Carry
endmodule // challenge
TestBench:
`timescale 1ns/100ps
module tb;
logic [2:0] SW;
logic [1:0] LED;
challenge u_challenge (.*);
// Stimulus
initial begin
$printtimescale(tb);
SW = '0;
for (int i = 0; i < 8; i++) begin
$display("Setting switches to %3b", i[2:0]);
SW = i[2:0];
#100;
end
$display("PASS: logic_ex test PASSED!");
$stop;
end
logic [2:0] sum;
assign sum = SW[0] + SW[1] + SW[2];
// Checking
always @(SW, LED) begin
if (sum !== LED[0]) begin
$display("FAIL: Addition mismatch");
$stop;
end
end
endmodule // tb
No matter what I put from SW into LED (any combination of SW[0],SW[1],SW[2]), I will always have my LED values set to X.
Is there a problem with my definition of SW?
