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I want to know the way to check the PCIe Memory-mapped BAR region is cacheable or not.

Is there any way to check the setting value or not? Or is it just configured uncacheable in hardware-way?? (I saw some post and articles that "MMIO memory region is always uncacheable" but I want to check or confirm the fact)

I configured PCIe device using the Xilinx FPGA and Xilinx PCIe IP. Also host cpu is Intel x86 Xeon CPU.

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  • It is controlled by the MTRR MSRs, page tables, the PAT MSR, and by EPT when in a guest. So you may have to check several places for a complete picture. See the Intel SDM, volume 3, chapter 12. Commented Mar 5, 2024 at 15:06
  • Although I may not be able to provide specific assistance, I am certain that the statement "The MMIO memory region is always uncacheable" is incorrect. Commented Jun 21, 2024 at 8:45
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