Synthesizable Verilog to dual write a 1-D flop array

Question

I'd like some Verilog (for synthesis) advice. I need dual writes to a 1-D array of flops. Both writes can occur on the same clock, and the write addresses will never be the same when the write enables are asserted.

My current code seems to simulate, (Synopsys VCS), correctly. I'm not sure if Design Compiler will crunch the correct gates. I'd greatly appreciate any advice.

// Both wr_en_a and wr_en_b can be asserted on the same clock.
logic        wr_en_a,   wr_en_b; 

 // wr_addr_a and wr_addr_b are never equal when wr_en_a and wr_en_b are both asserted.
logic [4:0]  wr_addr_a, wr_addr_b; 
                                  
logic [15:0] track_vec;

always_ff @(posedge clk) begin

  if (rst_q) begin
    track_vec <= '0;
  end

  else begin

    if (wr_en_a) begin
      track_vec[wr_addr_a] <= wr_en_a;
    end

    if (wr_en_b) begin
      track_vec[wr_addr_b] <= ~wr_en_b;
    end
  
  end

end

dave_59 · Accepted Answer · 2024-05-28 22:47:56Z

0

This is perfectly synthesizable even if both addresses are the same. Since this is within a single always process, last write wins. It would not work you split this into two always blocks.

answered May 28, 2024 at 22:47

dave_59

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Loucad Huang · Accepted Answer · 2024-06-02 04:36:33Z

-1

Be careful, your register is synchronize register

always_ff @(posedge clk) begin

if (rst_q) begin
  track_vec <= '0;
end

If you want to use asynchronize registers it should be like this

always_ff @(posedge clk or posedge rst_q) begin

if (rst_q) begin
  track_vec <= '0;
end

answered Jun 2, 2024 at 4:36

Loucad Huang

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