I'm currently studying computer architecture, following the Hennessy-Patterson books (Quantitative Approach 5 and Organizazion and Design 4), and I want to check if I'm understanding some cache functionality right.
The book states "Reads dominate processor cache accesses. All instruction accesses are reads, and most instructions don’t write to memory."
What I'm getting from this is:
- The fetch from the I-Cache counts as a read (1 memory access), and every instruction obviously has one during the IF stage
- Loads and Stores generate two memory accesses (the necessary I-Cache read during the IF stage, and a read or write to the D-Cache during MEM stage)
I think these two are given. Then my reasoning goes like this:
With the RISC design the books follow, only the Load and Store instructions interface with the memory (from cache upwards). Which means:
Only Loads and Stores can generate D-cache misses
Other kinds of instructions don't interact with the (main) memory at all (which should be a given, since it is one of the basics of the RISC approach), outside of the fetch from the I-Cache (which, I mean, technically is not an interaction generated by the instruction... You know?)
Writing to or reading from the register file doesn't count as a memory access. (Registers are obviously memory too, just "conceptually" separated in this case)
Instructions other than Load/Store can't generate D-cache misses because they don't interact with the memory system. Technically, those instruction don't even know about the memory system, all they know about is the register file.
The only instructions that can cause a I-Cache miss are the various jump and branch instructions (because by altering the PC, you might go too far for the I-Cache to hold instructions you need).
So if you're programming in assembly, you need to make sure that the data in the register file is what you need by loading it first (I'm ignoring data generated by other computations), because once you issue, say, a DADD instruction, it's gonna "assume" that the registers you point it to have the correct data to work on. Even, say, in the even that you turn on the CPU and the first instruction you issue at all is a DADD, with all the registers filled with garbage/0s, the DADD instruction is just gonna read that and proceed as normal (maybe crash). (I don't even know if this is possible but just go with it)
Also, just to be sure, in this MIPS implementation, Registers != I-Cache/D-Cache, right?
