VHDL Generic number concatenation of std_logic_vector

Question

I have an array of std_logic_vectors. The length of the array and std_logic_vectors are variable based on generics. How can I concatenate all the std_logic_vectors in my array without knowing the exact number of elements in my array?

Here's an example of what I need where I hard code the number of elements in the array:

  constant NUM_ELEMENTS  : integer := 3;
  constant VECTOR_LENGTH : integer := 2

  type t_small_vectors is array (0 to NUM_ELEMENTS-1) of std_logic_vector(VECTOR_LENGTH-1 downto 0);
  signal small_vectors : t_small_vectors;

  signal large_vector : std_logic_vector(NUM_ELEMENTS*VECTOR_LENGTH-1 downto 0);

begin
 
  large_vector <= small_vectors(2) & small_vectors(1) & small_vectors(0);

end architecture

This example doesn't work for me because I would need to change a line of code every time I changed NUM_ELEMENTS

I realize this has to fit in a generate statement or a for loop in a process but can't think through how it'd work.

Tricky · Accepted Answer · 2025-02-21 23:51:08Z

3

This is basically a type conversion. For this you will need a loop. For a specific case, you could use a generate loop

Large_vector_gen: For I in NUM_ELEMENTS-1 downto 0 generate
  large_vector((i+1)*VECTOR_LENGTH-1 downto i*VECTOR_LENGTH) <= small_vectors(i);
End generate;

But this is definitely something that could better be done in a function (this is vhdl2008)

Function to_long_vector( l : t_small_vectors ) return std_logic_vector is
  Constant VECTOR_LENGTH : natural l'element'length;

  Variable r : std_logic_vector(VECTOR_LENGTH*l'length-1 downto 0);
Begin
  For i in l'range loop
    R((i+1)*VECTOR_LENGTH-1 downto i*VECTOR_LENGTH) := l(i);
  End loop;

  return r;
End function;

edited Feb 21 at 23:51

answered Feb 21 at 22:23

Tricky

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2 Comments

user16145658 Feb 21 at 23:11

Between the question's pseudo code and your semantic errors one or both of you you should be dealing with code that can be validated. Here you don't specify the value for the constant VECTOR_LENGTH which is not specified in a package (and could be derived from the environment). Also R is not a signal, rather declared as a variable. Mixing upper and lower case letters in identifiers other than reserved words can obscure issues. Your function is also missing a return statement.

Aaron Linnell Feb 23 at 3:30

If you do use VHDL 2008, you might also benefit from subprogram instantiation, which can make a generic version of this answer's code.

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