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I am trying to understand the invalidating DMA buffers example from page D7-2450 in the Architecture Reference Manual ARMv7-A and ARMv7-R edition.

What is the memory barrier before the second invalidate for? What observable effects does the comment refer to? I thought there was none because the code did not write to [R1].

Why isn't there a memory barrier between the invalidate and the load? What guarantees that the load happens after the invalidate?

Why does the first memory barrier invalidate [R1] when the data are stored to [R3]?

DCIMVAC R1      ; ensure cache clean with respect to memory. A clean operation
                ; could be used but the DMA overwrites this region so an
                ; invalidate operation is sufficient and usually more efficient
DMB             ; ensures cache invalidation is observed before the next store
                ; is observed
STR R0, [R3]    ; send flag to external agent
WAIT ([R4]==1)  ; wait for a different flag from an external agent
DMB             ; ensure that cache invalidate is observed after the flag from
                ; external agent is observed
DCIMVAC R1      ; ensure cache discards stale copies before use
LDR R5, [R1]
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    The cache logic (MOSI, load/store unit, etc.) takes care of this [in this case r1 and r1 will ensure in order execution; r3 is not tied to r1, in the first case; r3 could be evicted (to core memory) before r1 and the DMA peripheral will be confused]. The DMA peripheral does not have this consistency logic. Depending on code and data MMU properties, this may/may not be needed. The example is probably for completely cached/buffered memories. Commented May 23 at 14:32
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