I was wondering if its possible to generate vhdl code from a schematic in xilinx. I know that the reverse is feasible. I want this to be done cause i am curious how the code will be like after i have completed the datapath of a mips R2000 and also its an easy way to modify large schematics by changing key lines in the code. I have used both schematics and vhdl but i d like to see the whole datapath written in a vhdl. I use Xilinx 12.3. Thanks!
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I do not know the answer to your question - but in my experience schematic to HDL conversion is typically very messy... Just as a warning. For your purposes (just modifying some key parts), it may work OK. But finding those "key parts" in the generated code could be difficult.Josh– Josh2012-01-25 23:26:48 +00:00Commented Jan 25, 2012 at 23:26
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1Have you looked at Active-HDL? I've not used this personally, another engineer at work mentioned it. aldec.com/en/products/fpga_simulation/active-hdlDavid Pointer– David Pointer2012-01-26 21:16:24 +00:00Commented Jan 26, 2012 at 21:16
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@DavidPointer Nop i havent tried it. I think that what i ask is not possible at least from what i ve found. Aldec seems to have nice editor vhdl combined with schematic. hmmm Does this mean that u can transform from code to schematic and vice versa?BugShotGG– BugShotGG2012-01-26 22:22:15 +00:00Commented Jan 26, 2012 at 22:22
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@GeoPapas I do not know, I've only heard about the product. Let us know what you find out if you decide to contact Aldec.David Pointer– David Pointer2012-01-26 22:41:25 +00:00Commented Jan 26, 2012 at 22:41
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1ActiveHDL allows the creation of block diagrams, which can automatically be turned into HDL code. A block diagram allows you to insert symbols, state machines (draw using state machine editor), etc and wire them together. I am not sure what you mean by "schematic" but this could be close to what you are looking for.Josh– Josh2012-01-27 16:29:10 +00:00Commented Jan 27, 2012 at 16:29
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3 Answers
The option is in the design menu -> select a .sch file in the implementation window and then click the "View HDL functional model". This will generate the vhdl code for the selected schematic. :o
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you can convert your schematic design into the HDL model. below the implementation under design, utilities tap to click on view HDL functional model which create the HDL file from the schematic which is .vhf for VHDL and .vf for the Verilog change this file into the .vhd for the VHDL and .v for the Verilog after then you can easily add this design into your vivado projects
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If you are using Vivado 2018.2, you can use write_vhdl in the Tcl console followed by the file's name to which you want to write the VHDL.
For example, write_vhdl Drive_Letter:\File_Location\Schematic_to_vhdl.vhd