I have a signal in VHDL declared like this :
signal Temp_Key : std_logic_vector(79 downto 0);
This Temp_Key is passed through a for loop 31 times and it is modified. I want to store all the 31 different Temp_Keys in an array.
Is it possible to use multi-dimensional arrays in VHDL to store 80 bit signals ?
Yes, first you need to declare a type:
type YOUR_ARRAY_TYPE is array (0 to 30) of std_logic_vector(79 downto 0);
Note you can also declare the type to be of undefined length - so you can specify how many 80 bit words it has when you declare your signal. And with VHDL 2008, you can also leave the size of the slv unspecified, also to be declared when you create your signal. For example:
type slv_array is array (natural range <>) of std_logic_vector;
and then use it
signal MY_SIGNAL : YOUR_ARRAY_TYPE;
...
MY_SIGNAL(0) <= data;
...
MY_SIGNAL(1) <= data;
See here for a reference.
Like the post above says, you can create any multi-dimensional array datatype. The other thing you need to be careful about is whether this code is synthesizable (i.e. targeted to FPGAs or ASICs, or is it purely for simulation). You can iterate from 0 to 31 using an FSM/counter or a generate block depending on how critical your timing is and how much area you are willing to use. A multi-dimensional array instance shown in above post is certainly synthesizable.
In VHDL there are two options
signal X is array (range) of ArrayType;
signal Y is array (range1, range2) of Type;
I think that option 1 is better supported by the tools. I also find similarity between these two options and the functional programming that teaches us that we can always curry a multivariate function (x,y) into a chain of single parameter ones, f(x) -> f(y). The latter looks like array of arrays.
