Syntax error near "else" in Verilog, in an initial block, next to assert

Question

I'm trying to make a self-checking testbench for an ALU I'm designing for an extra credit assignment. Here's what I have:

module testbench();
    wire [31:0] a, b, y;
    wire [2:0] f;
    wire zero;

    alu test(a, b, f, y, zero);

    initial begin
        a = 0; b = 0; f = 3'd2; #100;
        assert (y === 0) else $warning("0 + 0 failed");
        a = 0; b = 8'hFFFFFFFF; f = 3'd2; #100;
        assert (y === 8'hFFFFFFFF) else $warning("0 + FFFFFFFF failed");
        a = 1; b = 8'hFFFFFFFF; f = 3'd2; #100;
        assert (y === 0) else $warning("1 + FFFFFFFF failed");
        a = 8'h000000FF; b = 1; f = 3'd2; #100;
        assert (y === 8'h00000100) else $warning("FF + 1 failed");
    end
endmodule

I'm getting four critical warnings, all of them saying 'Syntax error near "else".', for each of the lines with the assert statements. I don't know why that's happening, I have the statements in the initial block. Does anyone know if I'm missing something here?

Are you using Verilog or SystemVerilog? There's a big difference. — Tom Carpenter
– Tom Carpenter, Commented May 1, 2020 at 19:46

dave_59 · Accepted Answer · 2020-05-01 20:03:12Z

1

You must use logic instead of wire. You cannot make procedural assignment s to wire signals.

You need to use 32'h instead of 8'h

Your file should have a .sv file extension; otherwise might be compiled with Verilog syntax rules.

answered May 1, 2020 at 20:03

dave_59

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