System Verilog code syntax error

Question

I wrote the following code:

module mul3 (
    input logic[1:0] d
);
mul3_op[0]=d[0];
endmodule;

But when I run it using Modelsim I get the following messages:

Error: (vlog-13069) mul3.sv(21): near "[": syntax error, unexpected '['.

Error: mul3.sv(21): (vlog-13205) Syntax error found in the scope following 'mul3_op'. Is there a missing '::'?

Please note that line 21 is actually the last line before endmodule in the code above. Any idea of what is wrong?

Mybe "input logic[1:0] d," and "output logic[3:0] res" should be "input [1:0]logic d," and "output [3:0]logic res". — Arseniy
– Arseniy, Commented Nov 27, 2020 at 12:24

Mitu Raj · Accepted Answer · 2020-11-27 12:40:49Z

2

You missed assign keyword for that concurrent statement -

assign mul3_op[0] = d [0] ;

answered Nov 27, 2020 at 12:40

Mitu Raj

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