Syntax error iverilog

Question

I don't know why I have a problem with compiling my Verilog code. I have these errors:

I have Icarus Verilog installed, and I checked it using the iverilog command. I also added the path for VSCode and for Iverilog.

Code:

`timescale 1ns/1ps 
`include "not_example1.sv" 

module testbench;
    parameter BITS = 4;
    logic [BITS-1:0] s_in;
    logic [BITS-1:0] s_model_outs;         
not_example1     #(.NUM(BITS))   not_model    (.i_a(s_in), .o_y1(s_model_outs));
    
initial
    begin 
        $dumpfile("signals.vcd");  
        $dumpvars(0,testbench);     

        s_in = '0;
        #1  s_in = '1;
        #1  s_in = '0;
        #1  s_in = '1;
        
        #1 
        $finish;
    end
endmodule

toolic · Accepted Answer · 2022-10-31 11:45:57Z

This warning message tells you that you should use the option named -g2005-sv when you run the iverilog command:

testbench.sv: warning: Using SystemVerilog 'N bit vector. Use at least -g2005-sv to remove this warning.

Some Verilog syntax, especially for features added to SystemVerilog (IEEE 1800), requires you to use special iverilog options.

This command fixes the errors and warnings for me:

iverilog -o testbench.vvp -g2005-sv testbench.sv

I have this version of iverilog installed:

iverilog -v
Icarus Verilog version 10.3 (stable) (v10_3)

To see the iverilog command usage, use the -h option:

iverilog -h
Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]
                [-g1995|-g2001|-g2005|-g2005-sv|-g2009|-g2012] [-g<feature>]
                [-D macro[=defn]] [-I includedir]
                [-M [mode=]depfile] [-m module]
                [-N file] [-o filename] [-p flag=value]
                [-s topmodule] [-t target] [-T min|typ|max]
                [-W class] [-y dir] [-Y suf] [-l file] source_file(s)

See the man page for details.

Also refer to the Icarus Verilog User Guide

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