Instantiating an array of modules in Verilog without using a loop

Question

Let's say I have a module called mymodule. I need to call it 10 times in my top_module file. I have seen someone on ResearchGate mention a method that uses the module instantiation as a vector (see Matt Weber's answer) and I tried doing the following:

mymodule [9:0]inst (inputs/outputs);

The tcl console threw a syntax error message stating the following:

Error (10170): Verilog HDL syntax error at top_module.v(8) near text: "(";  expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

But, when I did this:

mymodule inst [9:0] (inputs/outputs);

It successfully compiled and did what I wanted it to do, instantiate 10 modules without a loop.

What is this thing called? I tried searching for it online, and I saw nothing but for-loops inside a generate block.

The child module is not being called. This pattern is a model for inferring multiple instances of mymodule (fpga hardware). In synthesis workflows, additional physical resources (lookup tables, RAMs, ROMS, State Machines, PLL's, Ethernet Macs, FFT's etc) are used by each instance. — Mikef
– Mikef, Commented Sep 21, 2023 at 18:42

toolic · Accepted Answer · 2023-09-21 15:36:08Z

This is known as an instance array, or an array of instances. Refer to IEEE Std 1800-2017, section 23.3.2 Module instantiation syntax:

The instantiations of modules can contain a range specification. This allows an array of instances to be created. The array of instances is described in 28.3.5 (also see 23.3.3.5). The syntax and semantics of arrays of instances defined for gates and primitives apply for modules as well.

From section 28.3.5 The range specification:

There are many situations when repetitive instances are required. These instances shall differ from each other only by the index of the vector to which they are connected.

In order to specify an array of instances, the instance name shall be followed by the range specification. The range shall be specified by two constant expressions, left-hand index ( lhi ) and right-hand index ( rhi ), separated by a colon and enclosed within a pair of square brackets. A [lhi:rhi] range specification shall represent an array of abs(lhi-rhi)+1 instances. Neither of the two constant expressions are required to be zero, and lhi is not required to be larger than rhi . If both constant expressions are equal, only one instance shall be generated.

There is no need for a generate block in this case.

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