Questions tagged [computer-arithmetic]
Computer Arithmetic is the study of arithmetic algorithms and their hardware implementation. Use this tag when you ask questions on designing or verifying digital hardware for arithmetic functions.
40 questions
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How to find quotient at each step in binary division for hardware implementation?
The division principle is simply \$D = Q \cdot V + R\$,
where \$D\$ is a dividend, \$V\$ is a divisor, \$Q\$ is a quotient and \$R\$ is a remainder.
The pen-and-paper binary division algorithm works ...
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FPGA Fixed Point Arithmetic
I was currently reading this blog (highly recommended) about FPGA doing math (Doing fixed-point Math in FPGA).
But I am having some doubts while reading the second example (named ...
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Can consumer NPU hardware be repurposed?
Limiting this to the current generation of consumer NPU hardware going into new PCs:
Can the NPU accelerator hardware being put in recent PCs practically be repurposed for non-AI tasks? And what ...
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Applying analog computer with passive circuit only
TLDR
You can skip to question section.
Intro
I know the analog computer was actually invented long ago. I don't know how analog computer architecture was, but I guess it was using active components.
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How to perform addition operation in analog computing? [closed]
In digital computing, addition operations are commonly performed using circuits composed of logic gates, such as the full-adder circuit, which combines multiple bits to generate a sum along with a ...
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FPGA arithmetic implementation
How does an FPGA synthesis tool decide how to implement arithmetic operations on the target hardware?
For example, if I implement some integer multiplication and division operations directly in HDL ...
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Dissect code related to "Convergent rounding: Round half to even" written in SystemVerilog
This question is related to article on rounding found here.
The "Convergent rounding: Round half to even" code is written as follows:
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Why is this extra MUX here when shifting mantissa as part of a FP add?
My textbook (Harris and Harris, Digital Design and Computer Architecture) asks us to design a simplified (in that only positive numbers be considered, with NaN and infinities ignored) FP adder block. ...
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Is the Dadda multiplier faster than the Wallace multiplier?
If I understand it correctly, the Dadda multiplier adds the partial products in a similar way compared to the Wallace multiplier, but it doesn't reduce the partial product terms as much in its tree ...
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How many bits are needed to "fully capture" the addition of two binary integers?
(This is all related to my trying to understand my question here.)
Let's consider the addition of two n-bit integers, \$x = x_{n-1}...x_0\$ and \$y\$. Let their sum be \$s\$.
For the addition of ...
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How many bits are required for a quotient in binary division?
I saw somewhere that if we have A (dividend) which is 2n-bits and B (divisor) which is n-bit, we can store the quotient in n-bits with a specific condition: the (n-1)th bit of the divisor has to be 1.
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Arithmetic calculation error using PIC 18F4520 [closed]
I am trying to solve an equation using a PIC 18F4520 but the result that I am getting is not matching to the accurate answer that I calculated with Matlab.
The part of the equation is ...
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Is floating point IEEE754 binary digit represented using special unit/circuit for arithmetic operation?
We know that two un/signed integers arithmetic operation using special circuit called full-adder to execute arithmetic operation in Arithmetic Logic Unit (ALU).
The full-adder I mean is classical ...
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x86 MUL operation at hardware level
I understand the x86 operation to perform integer multiplication of two numbers (e.g. on 64 bits) is MUL.
My question is, how is this operation generally ...
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Floating point arithmetic - unexpected results in certain test cases
I was hoping I could get some help with a floating point adder I'm designing in verilog. The test case I am having trouble with is adding the following 2 numbers:
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Problem with the smallest negative number using Signed-2's-Complement
I have a problem figuring out why the smallest negative number we can represent in 3 bits, using Signed-2's-Complement is -4.
I understand that in S2C format, we can create numbers from 2x-1-1 (...
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Can BCD and binary multipliers share circuitry?
Suppose you are implementing a BCD multiplier. Google says there are reasonably efficient known circuits for this. Say 8x8 -> 16 digits, and trying for a reasonable compromise between speed and ...
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When are these adder algorithms used in digital circuit design?
Whenever I need to add two numbers, I just write a+b in VHDL. I never have to bother about what is synthesized, as long as timing and area constraint is met I think the objective is achieved.
I have ...
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How to do signed 16-bit arithmetic on an 8-bit processor?
For example, to add two 16-bit numbers on my 8 bit machine, I add the low bytes together, then the high bytes together, and then add the carry flag to the high byte of the output.
This strategy falls ...
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How to understand information as energy?
Cpu or gpu making calculations and creating information (decrease in entropy) is converting 100% of energy it pulls from the wall into heat.
How should we understand the created order in terms of ...
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Capturing overflow in twos complement addition
I am trying to implement 8-bit twos complement addition. I am doing this by splitting the 8 bit inputs into 4 bit parts and then implementing 4 bit complement addition.
A well known diagram is
where ...
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Verilog: Long expression — how to split into several steps with intermediate results?
The context is: I have 16-bit registers v1 and v2. These contain signed (2's complement) 16-bit values, but I decided to stay ...
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Is there a standard way to convert from a fixed point notation to a floating point notation?
Fixed point numbers can be in many different forms depending on the number of bits before and after the decimal expressed as Qm.n.
Floating point numbers can be in many forms depending on the number ...
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Problem while implementing a n-bit substractor circuit in python
I'm trying to implement the following substractor circuit in python:
And below is my code for it:
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Computer arithmetic algorithm: what might I be doing wrong?
So I'm working with the following differences equation:
$$y_n=\alpha y_{n-1}+(1-\alpha)x_n$$
I know this works with 16-fixed point arithmetic, and given some samples I'm trying to figure out how the ...
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Where did I code my multiplier wrong?
I've wrote a verilog code for Multiplier (8bit). I'm not getting the right result. Kindly tell me where i went wrong.
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How are irrational numbers best represented and processed by computers?
My question is closely related to this one: How do computers understand decimal numbers?
However, that question deals with rational numbers only. I was wondering if irrational numbers can be ...
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Multiplication of two binary numbers in fixed point arithmetic
I'm performing some operations with fractional numbers in a 16-bit FIXED-POINT processor.
I have to multiply the numbers \$ x=-6.35 \$, represented in \$ Q_{11} \$, and \$ y=-0.1 \$, represented in \$...
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Is it possible to build a binary divider with this design?
So I am working on this ALU, and I have made this 8-bit multiplier based on this design: . Is it possible to adapt this design into a binary divider by using Subtractors instead of Adders, and maybe ...
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Is it possible to create a reusable full subtractor in SystemVerilog?
I am trying to design a full subtractor in SystemVerilog.
I searched on Wikipedia and I found this https://en.wikibooks.org/w/index.php?title=Microprocessor_Design/Add_and_Subtract_Blocks
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Binary division restoring method
Hi i need help in understanding the binary division restoring method
From -2, we stored the value to 5 by adding the divisor which is 7
After adding 7 to get 5, why does it automatically jump to 10?
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FPGA multiplication using DSP hardware, signed vs. unsigned
I'm using the DSP unit (just a fancy name for the multiplier/accumulator unit) of the Gowin GW1N devices to do some fairly simple math. These units accept two 18 bit inputs for the multiplier adding ...
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Signed number multiplication on FPGA
I am trying to multiply signed numbers on a Nexys A7-100T FPGA development board with VHDL.
See Reference manual webpage link for the FPGA board hardware information.
Also see this link (begins page ...
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What is the fastest (in clock cycles) 16-bit x 16-bit unsigned integer division algorithm that will run on an ATMEGA1284?
What is the fastest (in clock cycles) division algorithm that will run on an ATMEGA1284?
The dividend is an unsigned 16-bit number passed into the algorithm in a pair of 8-bit registers.
The divisor ...
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Arithmetic right shift: a paradox?
So I was asked to perform the simple task of doing a 3-bit arithmetic shift of the number 1101 (-3 in 2's complement notation).
Now this is easy and it goes as 1101 -> 1110 -> 1111 -> 1111. ...
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How many logic gates does it take to implement base-100 addition?
I'm curious about the trade-offs that have been made in implementing different kinds of arithmetic in different models of computers, to which I'm trying to understand what the costs of various options ...
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Why is overflow error in two's complement addition represented by XOR-ing the last two carries?
The first chapter of my textbook on microcontroller theory has the following paragraph.
Here is one of the examples provided.
The book shows three such examples, but provides no explanation for why ...
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12-bit pipelined adder
I have been given the task of designing a 12-bit pipelined adder:
There are 4-bit adders connected by latches.
Why are latches used between the 4-bit adders? Is it for synchronization?
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Carry Look Ahead adder propagation delay calculation
I'm studying Digital Design and Computer Architecture book, I'm stuck in the section of the carry-lookahead adder because there's something that I don't fully ...
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Calculating the square root of 8-bit binary number
I was looking for a way to calculate the square root of a given 8-bit number using only digital combination or sequential logic. Is this possible?
One way may be to just use a look-up table since I'm ...
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