Skip to main content
Electrical Engineering

Questions tagged [configuration]

Ask Question

The tag has no summary.

120 questions
Newest Active Bountied Unanswered
Filter by
Sorted by
Tagged with
0 votes
1 answer
208 views

I'm wondering if it is possible to generate an PCIe x2 upstream port out of two PCIe x1 lanes as seen in the image below. Let me explain: The SOC provides one PCIe lane to the first packet switch. ...
bkausbk's user avatar
  • 304
0 votes
0 answers
174 views

We have developed a cyclone 10 Lp FPGA (10cl016Y) board, the Schematic is shown below The FPGA chip configures good through JTAG using .sof file, but if the Flash chip is programmed using .jic file, ...
Mohsin Shehzad's user avatar
  • 1
0 votes
1 answer
108 views

I am using HMC7044 IC for clock generation in my application design. Below is the evaluation schematic of HMC7044. HMC7044 has 14 clock outputs (7 DCLK outputs and 7 SYSREF outputs) and is mentioned ...
Sahasra Vaiishnavi's user avatar
  • 107
2 votes
2 answers
454 views

Can I get 12V to my system through USB type C without PD or configuration CC lines or Using CC controller? If yes how can I do that .
Vinod J's user avatar
  • 21
0 votes
1 answer
177 views

I've acquired an Altera FLEX 8282A FPGA and I'd like to have a bit of a play with it. Yes, I know these are prehistoric parts, but I like playing around with old stuff. :-) I've installed MAX+Plus II ...
Tom S's user avatar
  • 183
1 vote
0 answers
68 views

I'm having difficulties understanding how to configure the LIS2DE12 for generating interrupts. Especially the filter part is obscure to me. The task is to make the accelerometer generate an interrupt ...
Christoffer Kolbe Boye-Hansen's user avatar
  • 11
0 votes
0 answers
67 views

I am currently in the simulation phase of a controlled rectifier, and I must use CMOS technology. However, I am a novice in this field and would appreciate detailed advice to help me get started. ...
Manar HIMEUR's user avatar
  • 1
0 votes
1 answer
69 views

I have learned from my teacher that the input of the common gate is applied at the source pin and the output voltage is probed from the drain pin, why not vice versa? Can I do that?
Got's user avatar
  • 11
1 vote
0 answers
39 views

When I debug the code, the LCD refreshes rapidly. I am not confident with the correct system clock configuration to use. Moreover, after debugging, in release mode, nothing displays on my LCD nor the ...
Bravo's user avatar
  • 21
1 vote
1 answer
150 views

I'm trying to use the Schematic -> Defaults to predefine how I want every part of my schematic, but I found it a bit confusing. First of all, I can't make the changes that I want. Now I'm trying to ...
santiago deliotte's user avatar
  • 79
0 votes
1 answer
60 views

I was reading the XHP70 LEDs datasheet where there were two configurations given, 6V and 12V. I am having a confusion whether a single led is rated 6V/12V or a combination of LEDs are rated this way ...
kam1212's user avatar
  • 719
3 votes
1 answer
848 views

I am looking for assistance in editing my LTspice simulation for the design mentioned in the title. I have provided the design and output (open + short circuit) expectations (First two screenshots), ...
displayname6810's user avatar
  • 35
0 votes
0 answers
208 views

I'm checking the default configuration of an ethernet communication project based on STM32F2 microcontroller (stm32f207 RM0033 UM). Where the comments I'm gone to do, they could be find on section 28....
Suvi_Eu's user avatar
  • 891
4 votes
1 answer
264 views

I have designed a basic 8-bit CPU that is mapped onto FPGA fabric on a Digilent BASYS3 development board. The DRC results in a few error messages that I do not understand, with one of them being shown ...
David777's user avatar
  • 1,615
0 votes
1 answer
178 views

I was reading about USB specifications/configurations from this PDF. On page 5 it says that USB power configuration can be achieved (can be configured) with 3 different power options. I have utilized ...
Christianidis Vasileios's user avatar
  • 4,314
1 vote
1 answer
677 views

Using CubeIDE and configuring STM32L072 I get some (yellow triangle) GPIO conflicts on my I2C2 interface. The GPIO's are assigned to other non I2C uses. Where would I look to understand the ...
Peter Laidlaw's user avatar
  • 95
1 vote
1 answer
3k views

The Intel FPGAs have a number of different programming files, among these the files: .pof (Programmer Object File) .jic (JTAG Indirect Configuration) I know that the file .jic can be used to program ...
EquipDev's user avatar
  • 589
0 votes
1 answer
199 views

I'm looking for a dual color red/green LED that is not common-anode, not common-cathode, but common anode-cathode (anode of one LED shares a pin with the cathode of the other LED). Can anyone list a ...
Jess Stuart's user avatar
  • 1
2 votes
4 answers
594 views

While reading a research paper about enhanced coulomb counting, I found this peculiar sensing circuit (inside the red lines). (Research paper: Xie, Jiale, Jiachen Ma, and Kun Bai. “Enhanced Coulomb ...
A.H.Z's user avatar
  • 653
1 vote
2 answers
3k views

I have an ambiguity regarding the PCIe initial configuration which is performed by the root complex (RC) on the end-points (EP). Both devices have their own base address registers (BARs). The RC ...
malik12's user avatar
  • 135
4 votes
1 answer
1k views

I am working with some NetFPGA-SUME boards and I have an issue that is bothering me. This board contains a Xilinx Virtex-7 690T FPGA, a part that loads a configuration file into internal configuration ...
anmomu92's user avatar
  • 271
0 votes
1 answer
48 views

The both MFG no mentioned above has same datasheet? In datasheet they have mentioned like there is a programming for the configuration. Link: https://www.monolithicpower.com/en/documentview/...
Selva97's user avatar
  • 563
0 votes
0 answers
272 views

I am trying to implement the Shelly 1 switch for an electronic device I have. The electronic device has an open collector output channel (AUX1). It also has two output pins Z8 and C. When Z8 and C are ...
solutery7's user avatar
  • 1
1 vote
2 answers
428 views

I am using the Fusion360 New Electronics Library to reproduce the footprint/schematic of the NHS3152-AZ. Following along from Tutorial: Creating electronic components with Fusion 360, at min: 8:09 ...
Leo's user avatar
  • 261
0 votes
0 answers
122 views

I have a custom board with a new platform which does not have any tool to configure the DDR setup( I asked). I have the Source code for the uboot.config (CONFIG_DDR.c, CONFIG_DDR.h etc). So I have to ...
Aard's user avatar
  • 67
2 votes
1 answer
686 views

I'm working with a Microchip USB hub IC (USB2533 to be specific) and can't nail down a straightforward answer on how their configuration straps work through my own research. On this device, many pins ...
b.angle's user avatar
  • 73
1 vote
0 answers
38 views

In our system signal path, there is a clock signal being sent from the FPGA noted as SCLK. This goes to each component not including the MCU. The way I understand this is that the PLL receives the ...
JAlbers's user avatar
  • 55
0 votes
1 answer
268 views

So I wanted to program multiple FPGAs (different images) by using a processor over SelectMAP interfaces. I plan on sharing the PROG and INIT lines across the multiple images like this: This issue I ...
Matty's user avatar
  • 411
0 votes
1 answer
206 views

I am trying to implement a minimal partial reconfiguration project using the Vivado GUI. I have successfully enabled the project for reconfiguration and created a partition definition. The problem ...
Tom Hudson's user avatar
  • 3
1 vote
1 answer
1k views

When I first used the PCAP04 chip for measuring capacitance, I felt very annoyed, because the information on this chip was really a bit garbage. Many things are not found in the official manuals, and ...
Mbedded_oll's user avatar
  • 11
0 votes
2 answers
104 views

Say I have 4 unique resistors. How would I calculate all the possible unique series and parallel configurations and thus, calculate all the possible total resistances? And how can I expand this to ...
SidS's user avatar
  • 103
2 votes
2 answers
648 views

I am using 3 Artix-7 FPGAs in my design. Is it possible to use single SPI configuration Flash to program 3 FPGA device. I have found information about multiple boots for one FPGA but not multiple FPGA ...
Shifali's user avatar
  • 99
0 votes
1 answer
73 views

I am porting a working sequential circuit from a DE0-Nano to a DE5-Net. The circuit is driven by one global 50 MHz clock signal. The circuit only has one input and one output port for serial ...
Joey's user avatar
  • 3
0 votes
0 answers
204 views

During development work, JTAG is used to configure FPGAs. For the final version of the system there would be a few different options that will carry out automatic configuration of the FPGA actively or ...
gyuunyuu's user avatar
  • 2,347
2 votes
1 answer
141 views

The Melexis MLX90372 datasheet says that it can output either SENT protocol or PWM. I do not see anywhere in the datasheet how to put it into "PWM Mode" as they call it. Nor do I see how to ...
Aaron's user avatar
  • 9,213
5 votes
2 answers
814 views

Can someone help me to identify this VISHAY IC? Tips on how to do this are also welcome :). I could not find anything by searching with the numbers on top of the IC. The IC is used in a MKS 649B ...
Twan Vooijs's user avatar
  • 51
0 votes
1 answer
139 views

I've been thinking about this issue for a while now and came here for your guided assistance. Situation: Ik have 4 resistors (12V/1.25W heater pads). I need to power them with either a 12 or 24V ...
Jr.Maxwell's user avatar
  • 47
3 votes
2 answers
1k views

I have a BLDC motor on a controller I built running in both forwards and reverse. However the reverse direction is substantially noisier than the other and the motor vibrates more almost as if the ...
Simm's user avatar
  • 129
0 votes
1 answer
717 views

I've been thinking about motor designs and where all the power goes for an electric motor, especially in terms of used/unused power. I noticed that in most motor designs, the neodymium magnets float ...
FatalSleep's user avatar
  • 145
0 votes
1 answer
656 views

I am using code composer studio and using the microcontroller below, I used Energia software to run a simple program and it runs, but when I use CCS and try to flash an example program for this MCU ...
NAND's user avatar
  • 498
0 votes
0 answers
1k views

I am building a 5S6P battery with 18650 cells. I have limited space so the geometrical layout is constrained. I can think of 2 "optimal" ways to layout the cells connections but I don't know which is ...
Victor Lamoine's user avatar
  • 481
4 votes
2 answers
3k views

I'm studying semiconductor parameter analyzers. Those instruments are based on SMU (source and measuring unit) which can work either in the V-mode (they force a voltage on the device under test and ...
Stefanino's user avatar
  • 616
1 vote
0 answers
85 views

I recently read some papers that mentioned multicontext FPGAs, which have several copies of every programming bit. This allows to download a bitstream to the board while the active context (the ...
HastatusXXI's user avatar
  • 31
2 votes
3 answers
985 views

I am wokring on a board that uses Micron 1Gb QSPI (mt25qu01gbbb8e12-0aat) to load configuration on to FPGA at power on. As per the datasheet of QSPI (https://www.micron.com/-/media/documents/...
pmuppala's user avatar
  • 31
0 votes
1 answer
1k views

First I used MikroC for PIC to modify a firmware to a PIC18F4550. I was programming the device using MPLAB IPE and the PICKit3 programmer, everything was ok. Now, I need to change to MPLABX XC8 ...
Daniel's user avatar
  • 981
0 votes
1 answer
66 views

when a microcontroller communicates with another one via one of the communication protocols there is a configuration bit in a control register to choose whether to send(write) or receive(read) this ...
amgad's user avatar
  • 53
0 votes
1 answer
7k views

I have a USB 2.0 peripheral device based on an STM32 development board with hand-crafted code in C. This device works when connected to a Windows 7 computer but fails when connected to a Windows 10 ...
PeterE's user avatar
  • 11
0 votes
1 answer
213 views

I am working on a problem that can be made really simple if the output of the transistor were to be a fixed power of the input. For ex., if the input is 8 V and power is 0.333, then the output voltage ...
Ekdeep Singh Lubana's user avatar
  • 135
2 votes
2 answers
2k views

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...
quantum231's user avatar
  • 12.4k
0 votes
1 answer
363 views

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...
Anonymous's user avatar
  • 7,274

1
2 3