I have read that use of nonblocking assignments is not allowed in Verilog functions. Can anyone suggest a plausible explanation for this?
2 Answers
Try not to think about functions in Verilog like functions in C:
Functions in Verilog are designed to be a developer-friendly way to instantiate identical combinational logic in multiple places at once rather than having to write it over again / make a module for it. A lot of "newbies" to Verilog try to rationalize functions like they are C functions, and while they are "returning" a value, it is easier (and more correct) in the end to conceptualize them as blocks of combinational gates.
Note that this is different from a "task", which are more generally used for executing things "in order", which would probably be more useful in a testbench situation than a function
As you learn Verilog try not to rationalize the HDL you write as "code", because it is a different style of thinking.
EDIT: Took out some bad explanation on my part