I have a function f(), defined in a Verilog module, M1. I would like to reuse this same function in a different module, M2.
Is there anyway of doing this without redefining the function in M2?
--- M1.v ---
module M1();
function f;
//do stuff
endfunction
endmodule
--- M2.v -----
module M2();
// Use f() here
endmodule