Verilog: Store counter value when reset is asserted

Question

I have the following verilog code. Idea is to store value of counter at the time of reset. However, I am not sure if it would be synthesizable(memories need synchronous reset). I get DRC violatins and the memory, bufreadaddr, bufreadval are all optimized out. What are some other ways to write this?

module counter (clk,reset, d_out,laststoredvalue, bufreadaddr, bufreadval, resetcount) ;
input clk ,reset ;
input [5:0] resetcount;

output [15:0] d_out;
output [15:0] laststoredvalue;
input [5:0] bufreadaddr;
output [15:0] bufreadval;
reg [15:0] bufreadval;

reg [15:0] laststoredvalue;

reg [15:0] d_out;
reg [15:0] d_out_mem[63:0];

always @(negedge reset or posedge clk) begin
        if (reset == 0) begin
             d_out <= 16'h0000;
             d_out_mem[resetcount] <= d_out;
             laststoredvalue <= d_out;
         end else begin
              d_out <= d_out + 1'b1; 
          end
end

always @(bufreadaddr)
        bufreadval = d_out_mem[bufreadaddr];


integer count;
initial begin
  count = 0;
end
always @(posedge clk ) begin
    count = count + 1;
    //$display(count);
end


endmodule

This question was referenced here: danluu.com/why-hardware-development-is-hard — Victor Stafusa
– Victor Stafusa, Commented Jan 3, 2018 at 18:02

venkat pasumarti · Accepted Answer · 2016-09-22 10:24:50Z

hi i have made a small change for your code; added a temporary variable to store the output in a register it will store previous value on reset;

module counter (clk,reset, d_out,laststoredvalue, bufreadaddr, bufreadval, resetcount) ;
input clk ,reset ;
input [5:0] resetcount;

output [15:0] d_out;
output [15:0] laststoredvalue;
input [5:0] bufreadaddr;
output [15:0] bufreadval;
reg [15:0] bufreadval;

reg [15:0] laststoredvalue;
reg [15:0] temp;
reg [15:0] d_out;
reg [15:0] d_out_mem[63:0];

always @(negedge reset or posedge clk) begin
        if (reset == 0) begin

             d_out_mem[resetcount] = d_out;
             laststoredvalue = temp;
                 d_out  = #10 16'h0000;
         end 
            else begin

              d_out = d_out + 1'b1;
                    temp = d_out; 
          end
end

always @(bufreadaddr)
        bufreadval = d_out_mem[bufreadaddr];

endmodule

remaining code is same as it is.

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