Is this an acceptable way to code a non-resetable flop ?
input clk;
input b;
output a;
reg a= 1'b0;
always_ff @ (posedge clk)
if(b>a)
a<=b;
2 Answers
Non-resettable flops are used everywhere.....!
The technical advantage of resettable flop is that you can reach "known" state in a finite machine using a single transition on the reset pin else you might have to go through multiple cycles on the clock to reach a known state.
This is mainly needed when you power on the chip. There is trade off between "no of cycles needed" to the extra area that one has to pay for resettable flops.
Moreover, as mentioned at this page.
In case of flops without set/reset pin, the output is only deterministic if input D is in known stable state at the arrival of clock and satisfies the setup and hold requirement. During initial power up, the output of such flops will not be initialized and will be in unknown state, which is treated as X in the digital simulation. It remains X till the first clock edge comes and along with it comes the functional stable value at the input.
Following implementation in verilog and yours in SV is acceptable,
always @ (posedge sclk)
din_o <= din_i;
Keep in mind that, at declaration, even you don't assign it with 0, then also it works, but you will see X if you don't do. According to me it is bad habit to assign some variable at a time of declaration.
You have comparator, so until and unless your condition true, a remain X, but if you try as per above implementation(yours one) then, it will settled down to zero at power-on.
Silicon doesn't have X it has 1, 0 and Z only.
4 Comments
Matthew
It is certainly common to not reset a flip-flop I'm not sure I would go as far as saying flip-flops without resets have the highest usage in any design. I depends on the application. It also depends on the design rules. At my last company, all flip-flops were asynchronously reset. That was the rule. Doing so can make manufacturing test easier.
Matthew
And another thing... silicon can have
X: how would you describe the meta stable state of a flip-flop or the state of a net driven by two drivers pulling in opposite directions?
Prakash Darji
@MatthewTaylor: Yes! you are right, but my concern was, synthesis and simulation result mis-match.
Morgan
@MatthewTaylor I am not sure how I would describe those electrical effects. But when introducing people to Verilog and hardware design I often point out that x is unknown. At reset it is 0 or 1 but for simulation we just do not know. then they understand why you can not do
if (a == 1'bx) for Synthesis.This code describes a flop with an initial value. How that initial value is used is all down to the target. FPGAs will load that initial value into the register on reset. ASICs ignore the initial value. Simulators load initial values at time 0, but not on reset.
So, this code makes a register a which is either:
- Initialised to zero by the statement
reg a = 1'b0, but will ignore resets. This is the behaviour in simulation. - Reset to the value zero by the statement
reg a = 1'b0. This is the behaviour on an FPGA (and close enough in simulation if you only have a reset at the start). - Contains a random unknown value at reset, and hence the result of the comparison
a > bwill be unknown, and the circuit's behaviour will be unknown. This is the behaviour on an ASIC.
I suspect that the behaviour you're after is the second, as the other two aren't very useful. Note that to get predictable behaviour of the circuit you need to have the initial value loaded at reset, so this is a reset-flop, it's just you haven't explicitly written the code to observe reset.
A non-reset flop is one where we don't care about the initial state. For example a FIFO has registers which store the data passing through it, and registers which store the empty/full state of the FIFO. At power on, or reset, we care that the state of the FIFO is reset to empty, so the state registers must be reset. We don't care what the data registers contain because the FIFO is empty, so the data registers can be non-reset.
BTW the code you've written will always have zero in a, as a starts at zero and will never be greater than b. Therefore a will never be assigned to. I expect you meant the condition to be a < b, and the circuit to capture the maximum value of b
1 Comment
Sourabh
thanks @Paul for pointing out the error on checking condition.
reg a= 1'b0;implies a power up reset condition. It will be ignored for ASIC synthesis, potentially leading to RTL vs gate simulation mismatch.