the question is simple, I heared that assign out = (a>b)?a:b is wrong. is it wrong? if it is, is there another way to find MAX?
4 Answers
It's right if and only if out is a wire. If it's a register, then you have to do something like this:
always @* begin
if (a>b)
out = a;
else
out = b;
end
Take into account that in Verilog, a variable of type reg can infer either a wire or a latch, or a true register. It depends on how you specify the behaviour of the module that uses that reg:
Combinational (out is implemented as a wire although it's a reg)
module max (input [7:0] a,
input [7:0] b,
output reg [7:0] out);
always @* begin
if (a>b)
out = a;
else
out = b;
end
endmodule
Combinational (out is implemented as a wire and it's defined as a wire)
module max (input [7:0] a,
input [7:0] b,
output [7:0] out);
assign out = (a>b)? a : b;
endmodule
Latch (out is a reg, and it's implemented as a latch which stores the last produced result if conditions don't make it change, i.e. if a==b, which btw, may not provide a correct output in that case)
module max (input [7:0] a,
input [7:0] b,
output reg [7:0] out);
always @* begin
if (a>b)
out = a;
else if (a<b)
out = b;
end
endmodule
Register (out is implemented as a true register, clock edge triggered)
module max (input clk,
input [7:0] a,
input [7:0] b,
output reg [7:0] out);
always @(posedge clk) begin
if (a>b)
out <= a;
else if (a<=b)
out <= b;
end
endmodule
1 Comment
You can do this by using subtractor. Using a subtractor is less area cost expensive and faster - if fpga have sub/add components or arithmetic sub/add operation support and do not have comperator components.
https://polandthoughts.blogspot.com/2020/04/the-4-bit-signed-comparator.html
Check boolean function at the end. You check only 3 bits.
Sorry for my English.
3 Comments
(a>b)?