1

the question is simple, I heared that assign out = (a>b)?a:b is wrong. is it wrong? if it is, is there another way to find MAX?

4 Answers 4

3

It's right if and only if out is a wire. If it's a register, then you have to do something like this:

always @* begin
  if (a>b)
    out = a;
  else
    out = b;
end

Take into account that in Verilog, a variable of type reg can infer either a wire or a latch, or a true register. It depends on how you specify the behaviour of the module that uses that reg:

Combinational (out is implemented as a wire although it's a reg)

module max (input [7:0] a, 
            input [7:0] b, 
            output reg [7:0] out);
  always @* begin
    if (a>b)
      out = a;
    else
      out = b;
  end
endmodule

Combinational (out is implemented as a wire and it's defined as a wire)

module max (input [7:0] a, 
            input [7:0] b, 
            output [7:0] out);
  assign out = (a>b)? a : b;
endmodule

Latch (out is a reg, and it's implemented as a latch which stores the last produced result if conditions don't make it change, i.e. if a==b, which btw, may not provide a correct output in that case)

module max (input [7:0] a, 
            input [7:0] b, 
            output reg [7:0] out);
  always @* begin
    if (a>b)
      out = a;
    else if (a<b)
      out = b;
  end
endmodule

Register (out is implemented as a true register, clock edge triggered)

module max (input clk,
            input [7:0] a, 
            input [7:0] b, 
            output reg [7:0] out);
  always @(posedge clk) begin
    if (a>b)
      out <= a;
    else if (a<=b)
      out <= b;
  end
endmodule
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1 Comment

Is it safe to reason that the Register example can omit the "if (a<=b)"?
2

What you have there looks correct to me. There isn't really any other way to do it.

Comments

0

this works with 3 input values

module max(
    input [7:0] v1,
    input [71:0] v2,
    input [7:0] v3,
    output [7:0] max
    );

wire [7:0] v12;
wire [7:0] v23;

assign v12 = v1>=v2 ? v1 : v2;
assign v23 = v2>=v3 ? v2 : v3;

assign m = v12>=v23 ? v12 : v23;

endmodule

Synthesized

Comments

-1

You can do this by using subtractor. Using a subtractor is less area cost expensive and faster - if fpga have sub/add components or arithmetic sub/add operation support and do not have comperator components.

https://polandthoughts.blogspot.com/2020/04/the-4-bit-signed-comparator.html

Check boolean function at the end. You check only 3 bits.

Sorry for my English.

3 Comments

What is a comparator that evaluates (a>b)?
A subtractor is NOT a replacement for a comparator. If the difference is small (less than half the range of possible values) then the most significant bit might be usable as a compare bit. But if the difference is large (more than half the range of possible values) then the MSB is the opposite of the previous case.
@ceilingcat Having gone through the blogpost, you don't simply compare the MSB. It is a bit more involved than that. There are three conditions for the A>B case: 1) MSB == 0, 2) no underflow, and 3) the result is non-zero. So it is possible. Whether it is faster or not I do not know. It might be faster for larger numbers where you can some of the hardware features for addition/subtraction. Carry-chains or DSP slices.

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