Find the maximum of an input vector

Question

I'm trying to get the maximum of an input vector. I'm assuming all inputs are unsigned and that it should work on a range of bitwidths and array lengths. I have to keep the parameters and input and output logic the way they are. Here is what I have, but I get a syntax error at the if statement:

module max
 #(parameter int bW=16,
   parameter int eC=8)
  (input logic [bW-1:0] a[eC-1:0],
   output logic [bW-1:0] z);
  
 logic i=0;
 
 always @* begin

   for (i=0; i<size; i++) {
         if (a[i] >z)
             z = a[i];
       }
 end
endmodule

Maybe using a case statement would be better? I dont know.

dave_59 · Accepted Answer · 2017-05-04 15:24:42Z

1

Two simple problems.

You used brackets {/} instead of begin/end to wrap your looping statement. No need to wrap a single statement anyways.

You defined i as a single bit. use an int.

answered May 4, 2017 at 15:24

dave_59

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ajcrm125 · Accepted Answer · 2017-05-04 19:30:20Z

1

You'll also want to use a default for the initial value, then compute max from there.

For example:

module max
 #(parameter int bW=16,
   parameter int eC=8)
  (input logic [bW-1:0] a[eC-1:0],
   output logic [bW-1:0] z);

 always @(*) begin
   // defaults 
   z = 0;

   for (int i=0; i<size; i++) begin
       if (a[i] > z)
           z = a[i];
   end
 end
endmodule

answered May 4, 2017 at 19:30

ajcrm125

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Comments

toolic · Accepted Answer · 2025-10-02 10:22:20Z

1

In addition to the other answers, I believe the for comparison value should be 'eC', not 'size'. You never declared size. This compiles for me (with the "sverilog" flag of course):

module max #(
    parameter int bW = 16,
    parameter int eC = 8
)
(
    input  logic [bW-1:0] a [eC-1:0],
    output logic [bW-1:0] z
);

always @* begin

    z = a[0];
    for (int i=1; i<eC; i++) begin
        if (a[i] > z) begin
            z = a[i];
        end
    end
end
endmodule

edited Oct 2 at 10:22

toolic

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answered May 4, 2017 at 23:41

Matt H

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