How to get MAX or MIN in Verilog?

Question

I want to build a simple module to compare two 2-bit numbers and get the maximum number in the output.

I've used the code posted here: How to find MAX or MIN in Verilog coding?

module max (input [1:0] a, 
            input [1:0] b, 
            output reg [1:0] out);
  always @* begin
    if (a>b)
      out = a;
    else
      out = b;
  end
endmodule

But the problem I have, is that the output "out" does not give me a 2-bit number, and also the code is not working well as you can see in the screenshot.

This is the testbench I'm using:

`timescale 1ns/10ps
module maxTB();
reg [1:0] a, b;

max dut (.a(a),.b(b),.out(out)); 

initial
begin
a = 2'b1; b= 2'b0;
#20 a = 2'b10;
#40 b = 2'b11;
#50 a = 2'b01;
end
endmodule

modelsim screenshot

EML · Accepted Answer · 2015-12-29 18:11:32Z

4

You haven't declared out in your TB, so it has defaulted to a 1-bit net (a wire). This is a rather major failing in the language. To turn this behaviour off, add this outside any module:

`default_nettype none

answered Dec 29, 2015 at 18:11

EML

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