Generate frequency on FPGA

Question

I'm looking to generate a small signal from my FPGA. I'd like to output it through the stereo out on my board. The latter would act as a simple DAC. The following is a simple Verilog program that should play a beep but does not.

module music(clk, speaker);

input clk;
output speaker;

// Binary counter, 16-bits wide
reg [15:0] counter;

 initial 
    begin
    counter = 0;
    end

always @(posedge clk) counter <= counter+1;

// Use the most significant bit (MSB) of the counter to drive the speaker
assign speaker = counter[15];
endmodule

Ultimately I'd like to output a very low frequency sinusoidal wave through the stereo out. Is there any example code on how to do this...any ideas? I'm using a DE2i-150 board. Thanks!

isn't that what "reg[15:0] counter;" does? Can you please provide the code. — user2402616
– user2402616, Commented Feb 25, 2014 at 21:25
What is the clock frequency? Is the output waveform something in the audible spectrum? — Tim
– Tim, Commented Feb 25, 2014 at 21:28
The clock frequency is at 25MHz and the output should be a square signal around 380 HZ. — user2402616
– user2402616, Commented Feb 25, 2014 at 21:30

Community · Accepted Answer · 2017-05-23 12:32:26Z

4

I would use an async reset for initializing the counter:

module music(clk, _reset, speaker);

input clk, _reset;
output speaker;

// Binary counter, 16-bits wide
reg [15:0] counter;

always @(posedge clk or negedge _reset) 
    if (_reset == 1'b0)
        counter <= 'b0;
    else 
        counter <= counter + 1;

// Use the most significant bit (MSB) of the counter to drive the speaker
assign speaker = counter[15];

endmodule

testbench on edaplayground.

You can play with clock frequency and the upper limit of the counter to get the frequency that you want, i.e., rather than using the most significant bit, just write:

if (counter == UPPER_LIMIT) begin speaker = ~speaker; counter <=0; end

This only generates a square wave. In order to generate a sine wave, one easy way is to create a look-up table. See this.

edited May 23, 2017 at 12:32

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answered Feb 25, 2014 at 21:58

Ari

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3 Comments

Morgan Over a year ago

I believe the initial x=0 is preferred on FPGA due to limited Async reset flip-flops. While the async flip-flop is preferred on ASIC.

Ari Over a year ago

How about a sync reset? What exactly is an initial x=0 synthesized to? When a chip is powered up, its registers don't have a known value, and that is why one would need either a sync or an async reset. Granted, in some FPGA's downloading the bit file also initializes all memory elements, so one might get away without a reset signal, but that code would be FPGA and board specific. So I believe unless you are really short of area on your FPGA, you are better off using a reset signal. More on reset: eetimes.com/document.asp?doc_id=1278998

Morgan Over a year ago

a year ago I would have agreed, but reg x=0; or intial blocks do seem to be an accepted way of setting initial values for FPGA, and are often suggested on this site from those with much more FPGA experience than me.

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