Testing Verilog modules

Question

I'm new to Verilog programming and would like to test the following module. Can someone please point me in the right direction as far as where to get started with this? Do I just have to write a bunch of for loops to simulate all possible values for the four inputs and then use some display statements to see the result?

module HW7P1( A1, A0, B1, B0, O );
  input A1, A0, B1, B0;
  wire O;
  assign O = (!A1 & B1) | (!A1 & !A0 & B0) | (!A0 & B1 & B0);
endmodule

Community · Accepted Answer · 2017-05-23 11:49:22Z

1

Create a testbench module TB 101

Since the number of different inputs is small for you (16), you will be able to exhaustively check all of them.

You could sequentially step through all the input values with a for loop. It would be better to randomly assign the inputs ($urandom) in a loop.

You should create a checker module with a set of expected outputs for each input. Every time your input changes, you should check the actual output vs. your expected output. If they mismatch, you should $display an error message.

There are advanced verification methodologies available for doing this, such as UVM.

edited May 23, 2017 at 11:49

CommunityBot

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answered Mar 25, 2014 at 18:56

toolic

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