Testing multiple configurations of parameterizable modules in a Verilog testbench

Question

Say I have a Verilog module that's parameterizable like the below example:

// Crunches numbers using lots of parallel cores
module number_cruncher
    #(parameter NUMBER_OF_PARALLEL_CORES = 4)
    (input clock, ..., input [31:0] data, ... etc);
    // Math happens here
endmodule

Using Verilog 1364-2005, I want to write a testbench that runs tests on this module with many different values NUMBER_OF_PARALLEL_CORES.

One option that I know will work is to use a generate block to create a bunch of different number_crunchers with different values for NUMBER_OF_PARALLEL_CORES. This isn't very flexible, though - the values need to be chosen at compile time.

Of course, I could also explicitly instantiate a lot of different modules, but that is time consuming and won't work for the sort of "fuzz" testing I want to do.

My questions:

Is there a way to do this by using a plusarg passed in from the command line using $value$plusargs? (I strongly suspect the answer is 'no' for Verilog 1364-2005).
Is there another way to "fuzz" module parameterizations in a testbench, or is using a generate block the only way?

If you do not mind recompiling for every separate test, you can generated the constant using a script before compilation. Also, some compilers allow you to define parameters in a compilation switch. — Serge
– Serge, Commented Jan 11, 2022 at 18:37
Does the dut allow you to enable fewer cores than available? If so what is the difference between a 4 core all enabled and a 8 core half enabled? — Greg
– Greg, Commented Jan 12, 2022 at 5:19
@Greg this is just a silly hypothetical example. This is a great suggestion I hadn't thought of, but it's not applicable to every scenario. — John M
– John M, Commented Jan 12, 2022 at 17:01

toolic · Accepted Answer · 2022-01-11 17:30:08Z

2

Since $value$plusargs is evaluated at runtime, it can not be used to set parameter values, which must be done at compile-time.

However, if you use generate to instantiate multiple instances of the design with different parameter settings, you might be able to use $value$plusargs to selectively activate or enable one instance at a time. For example, in the testbench, you could use the runtime argument to only drive the inputs of a specific instance.

answered Jan 11, 2022 at 17:30

toolic

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