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According to Wikipedia, a structure containing a single byte and a four-byte integer, in this order, would require three additional bytes of padding because the four-byte integer has to be 4 bytes aligned.

  1. A structure containing a four-byte integer and a single byte, in this order, would require no additional padding bytes because one byte will be 1-byte aligned?

  2. The size of the first structure will be 8 but the size of the second structure will be 5?

  3. What about another four-byte integer allocated in memory after the second structure above? Will it be allocated after a gap of 3 bytes so that it respect the 4 bytes alignment?


[update from comment:]

I forgot to mention my example is on a 32 bit system.


[UPDATE]

I just found out that pack instructions added at the beginning and end of a structure only apply to the members of the structure and does not propagate to other structures. This means if you have a structure of structures, you have to pack them individually, not just the parent structure.

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  • Just to mess a bit with you, you can instruct most compilers to minimize or remove the padding as good as it can. Commented Jun 25, 2014 at 13:14
  • You mean instructing the compilers to "pack" the members of a structure to a certain level of alignment, e.g. "pack(2)"? Commented Jun 25, 2014 at 13:27
  • that is exactly what I am talking about :) Commented Jun 25, 2014 at 14:30
  • struct instances always use a multiple of the machine address size, and always start on an address boundary of the machine address size. UNLESS the pragma pack is used before the first struct instance. This also means that fields within the struct will contain padding so a field type is aligned (I.E. a int will be aligned on a 4 byte address boundary) Commented Jun 26, 2014 at 6:26
  • I just found out that pack instructions added at the beginning and end of a structure only apply to the members of the structure and does not propagate to other structures. This means if you have a structure of structures, you have to pack them individually, not just the parent structure. Commented Jun 26, 2014 at 8:15

2 Answers 2

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  1. Maybe, maybe not. You might be on an architecture that likes padding to 8-byte boundaries.
  2. Possibly. Never assume the same, predictable binary representation of a C structure across compilers. Or even across different options in the same compiler.
  3. Maybe. In the example architecture, probably. But the gap may in fact be larger if the compiler's libraries tend to allocate bigger chunks.
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4 Comments

I forgot to mention my example is on a 32 bit system.
It's still very much up to the compiler. And the across-the-board answer is "Probably, but right a test app and print out sizeof() for these structure to see."
Your answer is a bit confusing now that I specified the architecture. Unless instructed to pack the data at a certain alignment, on a 32 bit architecture, why would 2 compilers behave differently?
Because they can. They can pad a char to 1024K, if they choose (not that they would). The standard does not mandate structure alignment. A compiler might favor space efficiency; another might favor access speed and align everything to 32-bit boundaries; another might be tuned to the needs of its malloc libraries. You can assume all day, or you can test what your compiler is up to in your environment.
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A missing consideration in data alignment and packing is that there are at least 2 aspects of data alignment.

Performance: Certain alignments of types, like a 4-byte int often perform faster with an alignment on a matching (quad) address boundary. This is often a compiler default. Sometimes other lower performing alignments are possible. Compiler specific pack options may use this less optimal speed layout to achieve less padding.

Required: Certain alignments of types are required, like a 2-byte integer may cause a bus-fault on an odd address. Compiler specific pack options will not violate this. Packing may reduced padding, yet some padding may remain.


To answer OP's questions:
All are "maybe". It is compiler specific with consideration to its options and target hardware.

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