VHDL Input & output code

Question

I just started with VHDL so this is hopefully a pretty basic question, My problem is that i want to code this ciruit! --> http://postimg.org/image/rrd2czsox/ <--

In my ciruit as u can see, p and q both acts as input & outputs signal. Here is my code for this ciruit!

library ieee;
use ieee.std_logic_1164.all;


entity pracc is

port(a,b,s,p,q : in std_logic;
        y,z: out std_logic);

end pracc;

architecture Exercise5 of pracc is

begin 

p <= a AND b;
q <= NOT p;
y <= p;
z <= q;

end architecture;

But i can't compile this. Even if i change p & q as output signals!

Glad for help!

fru1tbat · Accepted Answer · 2014-09-03 14:51:27Z

1

p and q are not inputs to your overall circuit - they're intermediate/local signals. Declare them like so:

architecture ...
  signal p,q : std_logic;
begin
...

Local signals connect logic within a component. Ports connect your component to other things.

answered Sep 3, 2014 at 14:51

fru1tbat

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1 Comment

fru1tbat Over a year ago

Sure. Feel free to accept this answer if you feel it adequately answered your question.

user16270753 · Accepted Answer · 2021-10-16 11:26:39Z

0

Declare p,q as buffer instead of input or output.

Buffers are outputs that are again used to compute other outputs.

answered Oct 16, 2021 at 11:26

user16270753

1

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