Convert VHDL code to Verilog

Question

I have to translate the following vhdl program to verilog:

ENTITY ascounter IS
  PORT (CLK :IN STD_LOGIC;
      QoutA, QoutB, QoutC, QoutD :OUT STD_LOGIC);
END ascounter;
ARCHITECTURE circuit OF ascounter IS
   SIGNAL CLKnot, QBnot, QCnot, QDnot, QA, QB, QC, QD, HIGH :STD_LOGIC;
   BEGIN
      HIGH<='1';
      CLKnot<=NOT CLK;
      QDnot<=NOT QD; 
      QCnot<=NOT QC;
      QBnot<=NOT QB;
      FFD: JKFF PORT MAP (J=>HIGH, K=>HIGH, CLK=>CLKnot, CLRN=>HIGH, PRN=>HIGH, Q=>QD);
      FFC: JKFF PORT MAP (J=>HIGH, K=>HIGH, CLK=>QDnot, CLRN=>HIGH, PRN=>HIGH, Q=>QC);
      FFB: JKFF PORT MAP (J=>HIGH, K=>HIGH, CLK=>QCnot, CLRN=>HIGH, PRN=>HIGH, Q=>QB);
      FFA: JKFF PORT MAP (J=>HIGH, K=>HIGH, CLK=>QBnot, CLRN=>HIGH, PRN=>HIGH, Q=>QA);
      QoutA<=QA;
      QoutB<=QB;
      QoutC<=QC;
      QoutD<=QD;
END circuit;

and I have done it:

  ...
  assign HIGH = 1'b1;
  assign CLKnot = (~CLK);
  assign QDnot = (~QD);
  assign QCnot = (~QC);
  assign QBnot = (~QB);

 flipflop_jk FFD(.J(HIGH), .K(HIGH), .CK(CLKnot), .CLN(HIGH), .PRN(HIGH), .Q(QD));

 flipflop_jk FFC(.J(HIGH), .K(HIGH), .CK(QDnot), .CLN(HIGH), .PRN(HIGH), .Q(QC));

 flipflop_jk FFB(.J(HIGH), .K(HIGH), .CK(QCnot), .CLN(HIGH), .PRN(HIGH), .Q(QB));

 flipflop_jk FFA(.J(HIGH), .K(HIGH), .CK(QBnot), .CLN(HIGH), .PRN(HIGH), .Q(QA));

 assign QoutA = QA;
 assign QoutB = QB;
 assign QoutC = QC;
 assign QoutD = QD;

I have used a jk flipflop:

always @(CK or PRN or CLN)
 begin
  if (PRN == 1'b0)
  begin
     Q <= 1'b1 ; 
  end
  else if (CLN == 1'b0)
  begin
     Q <= 1'b0 ; 
  end
  else if (CK == 1'b0)  
  begin
     if (J == 1'b1 & K == 1'b1)
     begin
        Q <= ~Q ; 
     end
     else if (J == 1'b1 & K == 1'b0)
     begin
        Q <= 1'b1 ; 
     end
     else if (J == 1'b0 & K == 1'b1)
     begin
        Q <= 1'b0 ; 
     end 
  end 
 end

When I try to run the simulation, I get something like this which is wrong, but I cannot understand where the mistake is.

enter image description here

Does anyone have any idea?
Thank you very much!

You should add more info about what the problem is. "...which is wrong" isn't enough. — keyser
– keyser, Commented Oct 11, 2012 at 10:01
Thought that the x value in the output makes it obvious what is wrong. Apologies. — kasimoglou
– kasimoglou, Commented Oct 13, 2012 at 15:00

Morgan · Accepted Answer · 2012-10-11 13:44:53Z

It would be more appropriate to use edge sensitivity in the flipflop_jk definition, Also you have included an asynchronous clear signal, with a different value to your reset signal. My example shows this with a synchronous clear.

Your signal capture does not show your reset signal. I assume this is initially low then you take it high after time 0. To set Q to a known value.

module flipflop_jk(
  input      CK,
  input      PRN,
  input      CLN,
  input      J,
  input      K,
  output reg Q
);

always @(posedge CK or negedge PRN) begin
  if (PRN == 1'b0) begin
     Q <= 1'b1 ; 
  end
  else begin
    if (CLN == 1'b0) begin
      Q <= 1'b0 ; 
    end
    else if (J == 1'b1 & K == 1'b1) begin
      Q <= ~Q ; 
    end
    else if (J == 1'b1 & K == 1'b0) begin
      Q <= 1'b1 ; 
    end
    else if (J == 1'b0 & K == 1'b1) begin
      Q <= 1'b0 ; 
    end 
  end
end
endmodule

toolic · Accepted Answer · 2012-10-11 12:54:50Z

0

I assume you have declared Q as a reg in your jk flipflop module. By default in Verilog, a reg is initialized to x. Since the J, K, CLN and PRN inputs to your jk flipflop are tied high (1'b1), the only statement which is executed is Q <= ~Q ; (when CK goes low). Q remains unknown since the invert of x is still x. You never set Q to a known value.

edited Oct 11, 2012 at 12:54

answered Oct 11, 2012 at 12:49

toolic

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