Translating a VHDL code to Verilog compilation error

Question

I'm translating a VHDL code to Verilog but I have a question in VHDL: What is the use of the concatenation with the empty string in these lines?

Xp_m5b0 <= XX_m5(23 downto 0) & "";
Yp_m5b0 <= YY_m5(23 downto 0) & "";

It is said that it changes the type, but the types here are the same (std_logic_vector).

Here are the lines that showed the type:

entity IntMultiplier_LogicOnly_24_24_48_unsigned_F400_uid4 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(23 downto 0);
Y : in std_logic_vector(23 downto 0);
R : out std_logic_vector(47 downto 0) );
end entity;

signal XX_m5 : std_logic_vector(23 downto 0);
signal YY_m5 : std_logic_vector(23 downto 0);
signal Xp_m5b0 : std_logic_vector(23 downto 0);
signal Yp_m5b0 : std_logic_vector(23 downto 0);

XX_m5 <= X ;
YY_m5 <= Y ;

In verilog after translation, this concatenation gives a compilation error:

assign Xp_m5b0 = {XX_m5[23:0], 0'b }; 
assign Yp_m5b0 = {YY_m5[23:0], 0'b };

So does it have a difference in the meaning if I removed it and made it like this:

assign Xp_m5b0 = XX_m5[23:0]; 
assign Yp_m5b0 = YY_m5[23:0];

Removing the concatenation with a 0 0'b length value will not effect the result. — Morgan
– Morgan, Commented Feb 12, 2018 at 14:43
In VHDL Xp_m5b0 <= XX_m5(23 downto 0) & ""; is the equivalent of Xp_m5b0 <= XX_m5(23 downto 0); Concatenating two operands that are of the same single array type will result in the same type whose length is the sum of the lengths. (IEEE Std 1076-2008 9.2.3 Adding operators). The type of a string literal ("") is determined by context (9.3.2 Literals). The length of a string literal is the number of character values in the sequence represented. (15.7 String literals). — user1155120
– user1155120, Commented Feb 12, 2018 at 16:13

JHBonarius · Accepted Answer · 2018-02-12 14:54:20Z

1

"" is not an empty string, but an empty array. I haven't seen it used in this context, but it can be used to convert a literal to an array. I.e. consider the next code:

entity e is end entity;
library ieee;
architecture a of e is
    use ieee.std_logic_1164.all;
    signal a : std_logic_vector(0 downto 0);
    signal b : std_logic;
begin
    -- a <= b; -- fails
    a <= b&""; -- works
end architecture;

But since XX_m5(23 downto 0) is already an array (slice), it should not be required here...

answered Feb 12, 2018 at 14:54

JHBonarius

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