Can I use for loop in verilog `define statement?

Question

I need to include a rather complex computation in a verilog macro. Can I use for loop in Macro definition? Below is given the example of my code

`define CLOGB2(depth) \

      integer width \

      for(width=0;depth>0;width=width+1) \
        depth = depth >> 1; \

      return width


 module test #(parameter MEMDEPTH = 16)

         (
           // Input-output port declaration
         );

parameter MEMWIDTH = `CLOGB2(MEMDEPTH);

$display("Calculated width : %d\n",MEMWIDTH);

...

...

endmodule

Will it work?

Community · Accepted Answer · 2017-05-23 12:12:48Z

1

I think this question is largely a duplicate of How-to-define-a-multi-line-macro-in-verilog.

The reason for using the multi-line define or task in this question appears to be for a ceiling log2 function which is available by other means.

SystemVerilog & Verilog-2005

A built in $clog2() function is available

Verilog

Including you own function if $clog2 is not available may be simpler:

function integer CLog2;
  input   [31:0] depth;
  integer i;
  begin
    i = depth;
    for(CLog2 = 0; i > 0; CLog2 = CLog2 + 1)
      i = i >> 1;
  end
endfunction

edited May 23, 2017 at 12:12

CommunityBot

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answered Dec 19, 2014 at 9:08

Morgan

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