How to define clock input in Xilinx

Question

Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is due soon, where my partner, who was supposed to take care of the Xilinx simulations decided to bail on me. So here I am trying to figure it out last minute.

I have designed a synchronous counter using a few JK Flip Flops and I need to define the CLK input for the FJKCs.

I have drawn up the correct schematic, but I cannot figure out how to define a clock input.

Any help appreciated, and yes, this is homework. I just can't find any basic xilinx documentation/tutorials online and I honestly don't have time to learn the whole IDE.

I'm using VHDL

Verilog, VHDL? Come on man help us out.

ChaosPandion
– ChaosPandion

2010-05-03 14:27:48 +00:00
Commented May 3, 2010 at 14:27 — ChaosPandion
– ChaosPandion, Commented May 3, 2010 at 14:27
VHDL, sorry i'll edit the question

seventeen
– seventeen

2010-05-03 14:32:24 +00:00
Commented May 3, 2010 at 14:32 — seventeen
– seventeen, Commented May 3, 2010 at 14:32

StanislawSwierc · Accepted Answer · 2010-05-20 13:46:47Z

3

Imagine that you have a sample device as follows:

ENTITY SampleDevice IS 
    PORT 
    ( 
        CLK : IN std_logic
    );
END SampleDevice;

In order to attach CLK signal to a real clock input in your FPGA you should set it as Top Module and create an UCF file with an entry:

NET "CLK"  LOC = "P38";

The P38 is the clock input in Xilinx Spartan 3 XC3S200.

answered May 20, 2010 at 13:46

StanislawSwierc

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ChaosPandion · Accepted Answer · 2010-05-03 17:12:22Z

Check out this example.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;    -- for the unsigned type

entity counter_example is
generic ( WIDTH : integer := 32);
port (
  CLK, RESET, LOAD : in std_logic;
  DATA : in  unsigned(WIDTH-1 downto 0);  
  Q    : out unsigned(WIDTH-1 downto 0));
end entity counter_example;

architecture counter_example_a of counter_example is
signal cnt : unsigned(WIDTH-1 downto 0);
begin
  process(RESET, CLK) is
  begin
    if RESET = '1' then
      cnt <= (others => '0');
    elsif rising_edge(CLK) then
      if LOAD = '1' then
        cnt <= DATA;
      else
        cnt <= cnt + 1;
      end if;
    end if;
  end process;

  Q <= cnt;

end architecture counter_example_a;

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