How to use if statements in verilog

Question

I'm a total disaster at using verilog for implementing but this issue is walking on my nerves around an hour and I can't fix it!

here's my code

genvar i;
assign eq=1; 
assign gr=0;
generate for(i=7 ; i>=0 ; i=i-1)
        initial begin
        if(eq&&~gr)
            if (a[i]&~b[i])
              initial begin
               assign gr=1;
               assign eq=0;
              end
            else if (~a[i]|b[i])
            initial begin
              assign gr=0;

    assign eq=0;
    end
    end
endgenerate

the idea was to create some if statements so I could compare a[i] and b[i] if gr was 0 and eq was 1. the algorithm cannot be changed cause it's an assignment and I have to work this way but I'm really eager to find where the problem is (verilog's error description is not helping at all)

You cannot nest two initial blocks into each other. Get rid of the second initial keyword and just leave begin/end block. — Ari
– Ari, Commented Mar 11, 2015 at 21:24

Greg · Accepted Answer · 2015-03-11 21:53:58Z

1

generate blocks are used to replicate hardware at compile/elaboration time
initial blocks only run one at time 0. Changes to a and b will have no effect. It is illegal to nest initial blocks.
assign statements should not be used in initial blocks (it is legal but highly discouraged and is in consideration for depreciation). Generally a non-tri-state assign to a net should be done only once.
For continuous evaluation you need to use an always block

Best guess, this is the functionality you intended:

integer i;
reg eq,gr; 

always @* begin
  for (i=7 ; i>=0 ; i=i-1) begin
    if (eq&&~gr) begin
      if (a[i]&~b[i]) begin
        gr=1;
        eq=0;
      end
      else if (~a[i]|b[i]) begin
        gr=0;
      end
    end
    eq=0;
  end
end

answered Mar 11, 2015 at 21:53

Greg

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3 Comments

Farhood Over a year ago

hello and thanks for your amazing response! but I have a question here! I have faced these error and i don't know what to do! "LHS in procedural continuous assignment may not be a net: gr."

mcleod_ideafix Over a year ago

Means that you cannot assign a value to a variable defined as a wire, inside an always block. It has to be defined as a reg.

Farhood Over a year ago

how can i change the registers stored data? how can i give it a new number? I could not do that with "assign".

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