Multiple conditions in If statement Verilog

Question

I have the following if/else statement :

if ((write1 && write 2) && ( read_reg1== read_reg2))
      reg_file[write_reg1] =  write_data1;
    else if((write1 && write 2) && ( read_reg1!=read_reg2)) begin 
      reg_file[write_reg2] =  write_data2;
      reg_file[write_reg1] =  write_data1;
    end
    else if (write1)
      reg_file[write_reg1] =  write_data1;
    else 
      reg_file[write_reg2] =  write_data2;

I am getting these errors :

ERROR VCP2000 "Syntax error. Unexpected token: 2[_UNSIGNED_NUMBER]. Expected tokens: '[' , '(*' , '(' , 'with' , '++' ... ." "design.sv" 23  28
ERROR VCP2000 "Syntax error. Unexpected token: ). Expected tokens: '(*' , '++' , '--'." "design.sv" 23  58
ERROR VCP2000 "Syntax error. Unexpected token: 2[_UNSIGNED_NUMBER]. Expected tokens: '[' , '(*' , '(' , 'with' , '++' ... ." "design.sv" 25  31
ERROR VCP2000 "Syntax error. Unexpected token: ). Expected tokens: '(*' , '++' , '--'." "design.sv" 25  60
ERROR VCP2000 "Syntax error. Unexpected token: else[_ELSE]. Expected tokens: '#' , ''' , '(' , ';' , '@' ... ." "design.sv" 29  9

So what is the problem here ?

racraman · Accepted Answer · 2020-05-09 21:31:18Z

3

You have a space in your variable name.

write 2

Should be

write2

Note this occurs twice - in the “if” and the first “else if”

answered May 9, 2020 at 21:31

racraman

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megasplash · Accepted Answer · 2021-07-14 12:48:11Z

For someone who stumbles upon this question looking for a syntax reference, following are the excerpts from the sections "4.1.9 Logical operators" and "9.4 Conditional statement" in one of the revisions of the Verilog standard.

This is syntax of if statement:

conditional_statement ::= 
    if ( expression )
        statement_or_null [ else statement_or_null ]
    | if_else_if_statement

If the expression evaluates to true (that is, has a nonzero known value), the first statement shall be executed. If it evaluates to false (has a zero value or the value is x or z), the first statement shall not execute. If there is an else statement and expression is false, the else statement shall be executed.

And this is about logical operators to combine multiple conditions in one expression:

The operators logical and (&&) and logical or (||) are logical connectives. The result of the evaluation of a logical comparison shall be 1 (defined as true), 0 (defined as false), or, if the result is ambiguous, the unknown value (x). The precedence of && is greater than that of ||, and both are lower than relational and equality operators.

A third logical operator is the unary logical negation operator (!). The negation operator converts a nonzero or true operand into 0 and a zero or false operand into 1.

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