Verilog code works very well in Simulation but not on FPGA

Question

I having been trying to implement a simple sequence detector on a Nexys 3 (Spartan 6) board. The code works perfectly on Xilinx simulation but on the hardware, it doesn't work. Since I am new to FPGA implementation I couldn't solve this issue. I dont know what changes I should make for the code to work in hardware. It would be great if someone could help me..

And this is the code

    module sequence( in, clock,reset,test);
    input in;
    input reset;
    output reg test=0;
    reg [3:0] state=0, next=0 ;
    input clock;



    always@( posedge clock)
    begin
    if(reset==1)
    begin
    state= 0;
    end
    else
    begin
    state=next;
    end
    end

    always @*
    begin

    if(reset == 1)
    begin
    next=0;
    test=0;  
    end
    else
    begin

    case ( state )

    'd0 : begin
      if ( in==1)
             begin
                next=state+1;
                end

         else
         next=next;
         end

    'd1 : begin
      if ( in==1)
             begin
                next=state+1;
            end

         else
         next=0;
           end 

       'd2 : begin
          if ( in==1)
             begin
                next=state+1;
            end

         else
         next=0;
          end

     'd3 : begin
           if ( in==1)
             begin
                next=state+1;
            end

         else
         next=0;
          end

         'd4 : begin
               if ( in==1)
                 begin
                 next=state+1;
                test=1;
            end

         else
         next=0;
          end

      default : begin

                next=0;
                test=0;
            end

       endcase
       end
       end
       endmodule

Guy · Accepted Answer · 2015-03-26 17:24:47Z

1

I would change the beginning of your always block to:

always @*
begin
  next = state;
  test = 0;

  case (state)
    'd0 :
      begin
        if ( in==1)
          next=state+1;
      end
  ...

Setting a default assignment to all values in the state machine eliminates the possibility of creating an implicit latch. Your "next = next" statement shouldn't have any effect but might be creating latch (should probably be "next = state').

Also test is not assigned in every branch and has no default, so it will also create a latch.

answered Mar 26, 2015 at 17:24

Guy

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1 Comment

Jithin Sreenivasan Over a year ago

I tried using coregen to give the inputs and used chipscope to see the output directly from the hardware in my laptop and it works perfectly. Yet I still cant get the output in the hardware. I doubt that it must be because of the clock frequency of the hardware due to which I am not able to see the output. Is there any way to change the frequency of the clock available in the Spartan 6?

Jithin · Accepted Answer · 2015-03-26 19:16:42Z

The problems that I found in your Verilog code is given below.

Output variable test must be assigned in every case statement branches, else unwanted latches will form.
Use nonblocking assignments when you are specifying sequential circuit.

Try to code your sequence detector as below.

//sequence detector 101101

module fsm (rst,in1,clk,out1);

parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;

input rst,in1,clk;
output reg out1;

reg [2:0] state;

always @(posedge clk)
  if (rst)
    begin
      state <= s0;
      out1  <= 0 ;
    end
  else
      case(state)
              s0 : if (in1) begin state <= s1; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
              s1 : if (in1) begin state <= s0; out1 <= 0 ; end
                    else     begin state <= s2; out1 <= 0 ; end
              s2 : if (in1) begin state <= s3; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
              s3 : if (in1) begin state <= s4; out1 <= 0 ; end
                    else     begin state <= s2; out1 <= 0 ; end
              s4 : if (in1) begin state <= s1; out1 <= 0 ; end
                    else     begin state <= s5; out1 <= 0 ; end
              s5 : if (in1) begin state <= s1; out1 <= 1 ; end
                    else     begin state <= s0; out1 <= 0 ; end
        default: if (in1) begin state <= s0; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
      endcase

endmodule

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