vhdl code understanding, if there is modelsim error about possible infinite loop

Question

--
-- VHDL Architecture di_lib.ShiftRegister1.ShiftRegister1
--
-- Created:
--          by - 294162.UNKNOWN (VD1210)
--          at - 14:19:36 10-04-2015
--
-- using Mentor Graphics HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY WORK;
USE WORK.CALC_PKG.ALL;
LIBRARY di_lib;
USE di_lib.calc_pkg.all;
USE ieee.NUMERIC_STD.all;

ENTITY ShiftRegister1 IS
   PORT( 
      d_out       : OUT    Std_Logic_Vector (7 DOWNTO 0);
      multiplexer : IN     Std_Logic_Vector (7 DOWNTO 0);
      carry       : IN     std_logic;
      load_out    : IN     std_logic;
      f_code      : IN     std_logic_vector (2 DOWNTO 0);
      out_loaded  : OUT    std_logic
   );

-- Declarations

END ShiftRegister1 ;

--
ARCHITECTURE ShiftRegister1 OF ShiftRegister1 IS
BEGIN

  ShiftRegister1 : process

  variable remember, multiplexer_var       : std_logic_vector(7 DOWNTO 0);
  variable state          : std_logic_vector(2 DOWNTO 0);
  variable counter        : integer := 0; 
        begin

          state := f_code;

        case state is

        when "000" => 
            d_out <= multiplexer;

        when "001" =>
            d_out <= multiplexer;

        when "010" =>
                multiplexer_var := multiplexer;
            if load_out = '1' then 
              if carry = '1' then
                --shifting is done without function SRL
                remember(0) := multiplexer_var(1);
                remember(1) := multiplexer_var(2);
                remember(2) := multiplexer_var(3);
                remember(3) := multiplexer_var(4);
                remember(4) := multiplexer_var(5);
                remember(5) := multiplexer_var(6);
                remember(6) := multiplexer_var(7);
                remember(7) := '1';
                d_out <= remember;
                out_loaded <= '1';

              elsif  carry = '0' then
                remember(0) := multiplexer_var(1);
                remember(1) := multiplexer_var(2);
                remember(2) := multiplexer_var(3);
                remember(3) := multiplexer_var(4);
                remember(4) := multiplexer_var(5);
                remember(5) := multiplexer_var(6);
                remember(6) := multiplexer_var(7);
                remember(7) := '0';
                d_out <= remember;
                out_loaded <= '1';
              end if;
            end if;

        when "011" =>
            if load_out = '1' then
              d_out <= multiplexer;
              out_loaded <= '1';
            end if;

        when others => null;

        end case;
   end process;

END ARCHITECTURE ShiftRegister1;

--ERROR GIVEN --

-- Compiling architecture shiftregister1 of shiftregister1
**Warning: [2] <...>vhd(109): (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
Warning: Cannot create unmappedlibrary work

QUESTION: where possibly in this code an infinite loop can occur?

Jonathan Drolet · Accepted Answer · 2015-04-27 20:08:44Z

8

In VHDL, a process's execution time is instantaneous. Also, a process is re-executed as soon as it finishes. Thus your process forms an infinite loop.

To fix this, whether add a wait statement, or use sensitivity list. A process with a sensitivity list will only execute when one of sensitivity list signals changes. Something like:

process(load_out, carry, multiplexer, f_code)

You have to make sure to add all signals that the process uses on the sensitivity list, otherwise you will get a simulation mismatch, as sensitivity list is ignored for synthesis.

answered Apr 27, 2015 at 20:08

Jonathan Drolet

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1 Comment

Morten Zilmer Over a year ago

@Tomas: If this answers you question, then please accept the answer by clicking the check mark, as described here. See more in Help Center.

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