To Add if else statement into While loop VHDL

Question

I am trying to work on inserting if else to loop but it is still expecting some syntax. I cant figure out why this if/else statement wont compile. I am new to VHDL, please help. This is one of the steps along the way and i am stuck.


variable i : integer := 0;
    begin
        
        while i < 10 loop
            report "i=" & integer'image(i);
            i := i + 1;

    if i = 6 then
    report "okay good job";
    else i = 5 then
    report " okay nice work";
    else 
    report " not equal to 5 and 6";

        end loop;
        wait;
    end process;
end architecture;

IEEE Std 1076-1993 8. Sequential Statements, 8.7 If statement. in the BNF square brackets indicate optional items. sequence_of_statements ::= { sequential_statement }, where curly brackets indicate zero or more repetitions. Boldface denotes reserved words. — user1155120
– user1155120, Commented Mar 10, 2021 at 19:00

Tricky · Accepted Answer · 2021-03-10 10:22:45Z

2

In VHDL, the keywords are if, elsif and else

if condition_1 then
  -- do something
elsif condition_2 then
  -- do something else
else
  -- do something when all other conditions are false
end if;

answered Mar 10, 2021 at 10:22

Tricky

4,6083 gold badges15 silver badges32 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

To Add if else statement into While loop VHDL

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related