We know that the output of an FPGA is digital but can we genrate a pure analog sine wave using a vhdl code. also can I specify the frequency of the sine wav.
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for FPGAs and analog signals try electronics.stackexchange.commaxy– maxy2015-10-09 06:47:38 +00:00Commented Oct 9, 2015 at 6:47
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5 Answers
Define "pure" - how many "bits" of quantisation can you live with... and what frequency?
For lowish frequencies at lowish bits you could build a simple PWM or delta-sigma DAC in the FPGA and put a low-pass filter on the "outside" (sorry, that'll have to be real analogue hardware :) . This example may be informative
Not going to get there without some external componentry though.
3 Comments
SultanSh
Yes that what I thought about when I first talked about that but they said you could do it without any external ADC devices. They said you'll get the sine wave like it was generated from an analog generator without ripples and you can also chose the frequency of the sine wave.
Martin Thompson
Who's they? Is this an academic question, or a real-life problem? You really need to crank some numbers based on your requirements (in terms of sine frequency, quantisation etc.)
SultanSh
Thanx guys they told me that they were asking about generating it as adigital signal and to use dac after that but what I though that they want it without dac because they was so exciting that it is a very hard quistion sorry for that. :)
You can look into Direct Digital Synthesis. It basically uses a ROM to store the sine samples and uses a phase accumulator to index into the ROM to generate the output signal with the desired frequency. Resolution and maximum frequency is bound by the fpga clock and the ROM size.
You still need an anlog reconstruction filter, though.
Comments
The Method of generating Pure Sine waves from a previously stored samples in memory & reading the memory at varying rate / memory locations to change the frequency and or the spectral purity of the sine wave is called Direct Digital Synthesis.
This allows you to generate wide range of sine freq's with the required spectral purity. Useful in Mobiles & Software Defined Radio's & any other similar application. DDS ASIC's are also available but are usually expensive.
FPGA's are cheaper alternative. FPGA can only generate the required Digital output , but the analog singal cant be generated without a filter or a DAC & some basic filtering.
Most FPGA vendors have a free DDS IP Core with their IDE (Integrated Dev Environment). Checkout Actel/ Xilinx / Altera IP's. They're free. If you cannot manage to get an IP, you can pull a DDS function block in Matlab & utilize a 3rd party tool .. (available with all three above vendors) to synthesize a DDS via Matlab Interface . DDS is sometimes also known as DDFS : Direct Digital Frequency Synthesis.
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Except for a very few mixed-signal models (e.g. some Actel products), FPGAs do not have the components for the required analog reconstruction filter. They would have to be added on the outside.
Comments
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- use this library as much as possible.
entity sinewave is
port (clk :in std_logic;
dataout : out real range -1.0 to 1.0);
end sinewave;
architecture Behavioral of sinewave is
signal i : integer range 0 to 77:=0;
type memory_type is array (0 to 71) of real range -1.0000 to 1.0000 ;
--ROM for storing the sine values generated.
signal temp : memory_type :=(0.0,0.0872, 0.1736, 0.2588, 0.3420, 0.4226, 0.5000, 0.5736, 0.6428, 0.7071, 0.7660,
0.8191, 0.8660, 0.9063, 0.9397, 0.9659, 0.9848, 0.9962, 1.0000,0.9962,0.9848,0.9659,
0.9397, 0.9063, 0.8660, 0.8191, 0.7660, 0.7071, 0.6428, 0.5000, 0.4226, 0.3420, 0.2588,
0.1736, 0.0872,0.0, 0.0,-0.0872,-0.1736, -0.2588, -0.3420,-0.4226, -0.5000, -0.5736,
-0.6428, -0.7071, -0.7660, -0.8191, -0.8660, -0.9063, -0.9397, -0.9659, -0.9848, -0.9962,
-1.0000,-0.9962,-0.9848,-0.9659,-0.9397, -0.9063, -0.8660, -0.8191,
-0.766, -0.7071, -0.6428, -0.5000, -0.4226, -0.3420, -0.2588, -0.1736, -0.0872,0.0);
begin
process(clk)
begin
--to check the rising edge of the clock signal
if(rising_edge(clk)) then
dataout <= temp(i);
i <= i+ 1;
if(i = 71) then
i <= 0;
end if;
end if;
end process;
end Behavioral;
Solve this implementation It shows error than constant value expected for expression 1.000
