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I am working on a project in VHDL wich includes mutliplying matrices. I would like to be able to load data from PC to arrays on FPGA using UART. I am only making my first bigger steps in VHDL and I am not sure if I am taking the right attitude.

I wanted to declare an array of integer signals, and then implement UART to receive data form PC and load it into those signals. However, I can't use for-loop for that, as it will be synthesised to load data parallelly (which is impossible, because values will be comming from PC one after another, using serial port.) And because matrices may be various sizes, in order to assign signals one by one I would need to write lots of specific code (and it appears to be a bad practice to me.)

Is the idea to use an array of signals and load data to those signals through UART realizable? And if my approach is entirely wrong, how could I achieve that?

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What you want is doable but you will probably need to design a kind of hardware monitor to act as an intermediate between your UART and your storage (your array of integer signals). This hardware monitor will interpret commands coming from the UART and perform read/write operations in your storage. It will have one interface with the storage and another with the UART. You will have to define a kind of protocol with a syntax for your commands and of sequences of operations for each command.

Example: the monitor waits for commands coming from the UART. The first received character indicates whether it is a read (0) or a write (1). The four next characters are the target address, least significant byte first. If the command is a read, the monitor reads the data at the specified address in your storage and sends it to the UART, one byte at a time, least significant byte first. If the command is a write, the address is followed by a data to write in your storage at the specified address, least significant byte first, and your monitor waits until the data is received and writes it in your storage.

Optionally, the monitor could send an exit status byte at the end of each command to indicate potential errors (protocol errors, unmapped addresses, write attempts in read-only regions...)

Of course, depending on the characteristics of your application, you will probably define a completely different protocol, simpler or more complex, but the principle will be the same.

All this is usually implemented in software and runs on a CPU that has the UART as peripheral and the storage in its memory space. But if you do not have a CPU...

Warning: this is quite complex. The UART itself is quite complex. Not sure you should start with this if you are a VHDL beginner.

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Thanks a lot! I was wondering if there was any way to have like-software loop for indexes? (I know the order of sent elements in advance, so that I would not need to send address for every value)
That's why I wrote that your protocol will be very different: you know more about your application than I do. Of course, if you send all data in a fixed order, you can generate the addresses internally with a counter. But this will not really be a software-like loop. It will be a register that will have to be incremented at some points that you will have to decide. And you will also have to decide when to re-initialize the counter before processing the next command.
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Your approach is not entirely wrong but you have a software orientated way of expressing this which indicate you are missing the fundamentals. People with strong software backgrounds tend to think in terms of the programming language and not in terms of the actual FPGA specific structures they want to achieve. It is the important to unlearn this if you want to be successful in designing for FPGA.

Based on what I just wrote you should consider in what type of FPGA structure you would like to store the data. The speed, resource and power requirements govern this choice. One suitable way to store the data would be in either a single or an array of either Block RAM or LUTRAM. Both of these structures can be inferred by using a signal of an array type in the hardware description language which is why I said you are not entirely off track. Consult the manual of your synthesis tool to find templates for how to infer these structures. An alternative is to use a vendor IP block or to instantiate a primitive directly but both those methods are clumsier in my opinion.

Important parameters to consider are the total number of words you need to store, the size of a word and the number of read/write operations per clock cycle. For higher number of reads per cycle an array of memories must be used since most FPGA memories only support two reads per cycle.

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Thanks for your advice. One thing is that I actually need to store that data in FPGA's logic, rather than RAM (I want to perform parallelized multiplication, so accessing values one by one is not an option here.)
If you want to access all values simultaneously you have to use plain old FPGA registers. Those can also be inferred by using a signal or variable of an array type in the HDL. If your HDL uses many or all values in the same cycle the synthesis tool will be forced to implement it as a pile of FPGA registers.
I do not know how big your matrices are but doing all multiplications at once is most of the time not a good solution. Maybe for 2x2 or 3x3 matrices it is reasonable. For a 10x10 matrix it would be very unreasonable in most applications. Remember that there is no point in computing faster than you can get data in and out of your compute blocks. Can you load all 10x10 matrix elements every cycle? For a 10x10 matrix multiplication it might be better to store data in an array of LUTRAMS such that partial blocks or rows of the matrices can be operated on in parallel.
I believe you are exaclty right. Thing is this is a scientific project, simulating something. So while performance is not exactly critical here, parallel multiplication is. Thanks for your hints!

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