genvar is missing for generate "loop" variable : verilog

Question

Getting error 9: error: genvar is missing for generate "loop" variable 'r'. 1 error(s) during elaboration.

The entire code:

module divider (dividend, divisor, quotient, remainder ) ;
    input [7:0] dividend ; // eight input lines modeled as a bus
    input [7:0] divisor ; // select lines bundled as a bus
    output reg [7:0] quotient ;
    output reg [7:0] remainder ;
    reg [7:0] r;
    reg [7:0] q;
    assign q = 0;
    for(r = dividend; r >= divisor; r = r - divisor)
        assign q = q + 1;
    assign remainder = r;
    assign quotient = q;
endmodule

module main;
    reg [7:0] dd;
    assign dd = 12;
    reg [7:0] dr;
    assign dr = 5;
    reg [7:0] q;
    reg [7:0] r;
    wire a = divider(dd, dr, q, r);
    initial begin
    $display("quotient %d", q);
    $display("remainder %d",r);
    end
endmodule

I'm trying to write a module to calculate quotient and remainder by repeated subtraction using behavioral modeling in verilog. This is my first verilog program and I'm having trouble fixing these errors, please point out if there are any other errors in my code.

ssgr · Accepted Answer · 2015-10-16 10:04:15Z

2

The problem is with the for loop. You can either use generate block or always block to use it. One of the way to do is as follows :

module divider (dividend, divisor,quotient, remainder ) ;
input [7:0] dividend ; // eight input lines modeled as a bus
input [7:0] divisor ; // select lines bundled as a bus

output reg [7:0] quotient ;
output reg[7:0] remainder ;

 always @(*) 
  begin
       quotient=0;
       for(remainder = dividend; remainder >= divisor; remainder = remainder - divisor)
          quotient = quotient + 1;            
  end

endmodule



module main;

reg[7:0] dd; 
reg[7:0] dr;

wire [7:0] q;
wire [7:0] r;

divider d0( .dividend(dd), .divisor(dr), .quotient(q), .remainder(r) ) ;

initial begin
   dd=12;
   dr=5;
end

initial begin
 #20  $display("quotient %d", q);
 #25    $display("remainder %d",r);
end

endmodule

Few things to note:

If you wan to assign a variable using assign statement, declare that variable as wire.
In the testbench, you need to define inputs as "reg" and outputs as "wire".
You cannot use assign in for loop.

edited Oct 16, 2015 at 10:04

answered Oct 16, 2015 at 6:56

ssgr

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3 Comments

Unn Over a year ago

The code you provided for the divider logic will not work as intended as you use NBA in the loop. This means that it will NOT update quotient on each loop, but instead only result in quotient being set to 0 or incremented from its previous value, which in your case was from the previous attempt to divide. Also, you use blocking assignment for remainder in a clocked always block, which result in simulations that do not properly simulate real hardware.

ssgr Over a year ago

@Unn I found my mistake :) . Will it be a problem at the hardware level if I use all blocking assignments in always block? Because it works fine at the simulation level if I convert NBA to blocking assignments .

Unn Over a year ago

While this setup might appear to be working fine with blocking assignment, as soon as you integrate it into a design that uses quotient or remainder in some other module or block, simulation will have a race condition. To accurately simulate hardware, you need to use NBA in clocked blocks (and BA in combinational blocks like always @(*)). Synthesis tools usually can figure it out if you use BA; but you should never use BA in clocked blocks.

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