Verilog loop sequentially for each iteration of the loop

Question

I have created a module that is this:

module testX(input [6:0]n, input [6:0]offset, output result);

I want to run this module increasing the offset until result returns a specific condition. When I use a loop, the code is compiled so all of the iterations run at the same time like normally synthesized code.

I want to make testX use all the resources of the FPGA and then by changing the offset loop it multiple times in order to make a massive parallel application.

I understand that loops are not to be used like this according to this source, so how would I accomplish something like this? In a normal programming language, I would just do something like this:

while result==0
   testX(n,offset,result)
   offset=offset+C
end while

Another side question is how would I know then the testX operation is complete? Would I need a status variable to indicate it was finished and to change the offset when I saw that the status changed?

Note: This could probably be done with a clock and always statement also, but I am looking for a asynchronous method.

A Verilog module is not a SW function; you do not run it; you cannot "call" it from within a loop. A Verilog module is a piece of HW; it exists for all time. — Matthew
– Matthew, Commented Mar 6, 2016 at 21:25
I under stand that. My goal if to feed different offsets into my module, and look at the result pin to see if it got a result, and output that to a pin. — Eric Johnson
– Eric Johnson, Commented Mar 6, 2016 at 21:36
In this way, the testX would always exist, but an adder would increment offset as it would continue to loop. — Eric Johnson
– Eric Johnson, Commented Mar 6, 2016 at 21:37
I started writing up an answer, but then realised I still don't understand your problem. I was going to suggest instantiating many copies of testX inside a generate loop, but you say that testX takes all the resources of the FPGA, so there can only be one instance. In which case, it needs to be time-multiplexed, but then you say you want to make it asynchronous. (Do you mean "combinational" rather than "asynchronous"?) — Matthew
– Matthew, Commented Mar 7, 2016 at 9:28
What I mean by asynchronous is that as soon as the operations in testX finish, it either changes the clock or the offset variable so there is no time waiting for a clock. With Greg's answer he says it would not function properly doing this. — Eric Johnson
– Eric Johnson, Commented Mar 8, 2016 at 11:46

Greg · Accepted Answer · 2016-03-08 04:39:34Z

1

You need to time-plex the change to offset like below. Hardware will not function properly with complex asynchronous feedback.

always @(posedge clk) begin // time-plexing
  if (result==0) begin
     offset <= offset+C; // inside a procedural block, non-blocking assignment
  end
end

testX(n,offset,result); // outside any procedural block

answered Mar 8, 2016 at 4:39

Greg

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