After compiling a project (with Quartus) with a top-level file (VHDL) and an Altera specific PLL, I tried to simulate it with ModelSim.
When I start the RTL simulation, I see my top-level file in the folder work (in the Library Window), but not the Altera instance for the PLL (Verilog file).
Question: How can I setup Quartus or ModelSim in order to see my top-level file AND the Altera instance for the PLL?
The Altera specific modules like PLLs, are easiest to simulate using the ModelSim Altera Edition (available with Altera Quar5us) which contains a number of pre-compiles libraries with packages and entities for the Altera specific blocks. If not already using this ModelSim Altera Edition. You can see the Altera libraries in the ModelSim Altera Starter Edition (free) below.
Then you simply compile all the modules into a library, including the Altera Quartus generated wrapper for the PLL, the wrapper should then have references to the available Altera libraries with the simulation model of the PLL.
If this does not work, then please reduce your code to an example that shows the problem and can be posted here; see Minimal, Complete, and Verifiable example.
Just compile like you would any vhld/verilog source code:
vcom *.vhd
vlog *.v
vlog -sv *.sv
The simulation models are available with Quartus install. Assuming you have Quartus installed at QUARTUS_DIR for example, to compile some VHDL simulation models you'd do:
vlib work;
vcom -work work QUARTUS_DIR/eda/sim_lib/altera_mf_components.vhd
vcom -work work QUARTUS_DIR/eda/sim_lib/altera_mf.vhd
You'd need to pay attention to the order of compilation in most cases. You can create an Altera model simulation library and then just map it so that you don't have to compile the same code for each of your projects.
